C8051F120 Datasheet, PDF (11/356 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
Figure 7.13. ADC2LT: ADC2 Less-Than Data Byte Register................................. 104
8. DACs, 12-Bit Voltage Mode (C8051F12x Only) .................................................. 107
Figure 8.1. DAC Functional Block Diagram............................................................ 107
Figure 8.2. DAC0H: DAC0 High Byte Register ...................................................... 109
Figure 8.3. DAC0L: DAC0 Low Byte Register........................................................ 109
Figure 8.4. DAC0CN: DAC0 Control Register........................................................ 110
Figure 8.5. DAC1H: DAC1 High Byte Register ...................................................... 111
Figure 8.6. DAC1L: DAC1 Low Byte Register........................................................ 111
Figure 8.7. DAC1CN: DAC1 Control Register........................................................ 112
9. Voltage Reference ................................................................................................ 115
Figure 9.1. Voltage Reference Functional Block Diagram (C8051F120/2/4/6) ...... 116
Figure 9.2. REF0CN: Reference Control Register (C8051F120/2/4/6) .................. 116
Figure 9.3. Voltage Reference Functional Block Diagram (C8051F121/3/5/7) ...... 117
Figure 9.4. REF0CN: Reference Control Register (C8051F121/3/5/7) .................. 118
Figure 9.5. Voltage Reference Functional Block Diagram (C8051F130/1/2/3) ...... 119
Figure 9.6. REF0CN: Reference Control Register (C8051F130/1/2/3) .................. 119
10. Comparators ......................................................................................................... 121
Figure 10.1. Comparator Functional Block Diagram .............................................. 121
Figure 10.2. Comparator Hysteresis Plot ............................................................... 123
Figure 10.3. CPT0CN: Comparator0 Control Register ........................................... 124
Figure 10.4. CPT0MD: Comparator0 Mode Selection Register ............................. 125
Figure 10.5. CPT1CN: Comparator1 Control Register ........................................... 126
Figure 10.6. CPT1MD: Comparator1 Mode Selection Register ............................. 127
11. CIP-51 Microcontroller ......................................................................................... 129
Figure 11.1. CIP-51 Block Diagram....................................................................... 130
Figure 11.2. Memory Map ...................................................................................... 136
Figure 11.3. PSBANK: Program Space Bank Select Register ............................... 137
Figure 11.4. Address Memory Map for Instruction Fetches (128k byte FLASH Only)..
137
Figure 11.5. SFR Page Stack................................................................................. 140
Figure 11.6. SFR Page Stack While Using SFR Page 0x0F To Access Port 5...... 141
Figure 11.7. SFR Page Stack After ADC2 Window Comparator Interrupt Occurs . 142
Figure 11.8. SFR Page Stack Upon PCA Interrupt Occurring During an ADC2 ISR....
143
Figure 11.9. SFR Page Stack Upon Return From PCA Interrupt ........................... 144
Figure 11.10. SFR Page Stack Upon Return From ADC2 Window Interrupt ......... 145
Figure 11.11. SFRPGCN: SFR Page Control Register .......................................... 146
Figure 11.12. SFRPAGE: SFR Page Register ....................................................... 146
Figure 11.13. SFRNEXT: SFR Next Register......................................................... 147
Figure 11.14. SFRLAST: SFR Last Register.......................................................... 147
Figure 11.15. SP: Stack Pointer ............................................................................. 155
Figure 11.16. DPL: Data Pointer Low Byte............................................................. 155
Figure 11.17. DPH: Data Pointer High Byte ........................................................... 155
Figure 11.18. PSW: Program Status Word............................................................. 156
Figure 11.19. ACC: Accumulator............................................................................ 157
Rev. 1.3
11