C8051F120 Datasheet, PDF (311/356 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
Table 22.4. Timer Settings for Standard Baud Rates Using the PLL
Frequency: 50.0 MHz
Target
Baud Rate
(bps)
Baud Rate Oscilla-
% Error tor Divide
Factor
Timer
Clock
Source
230400
115200
57600
28800
14400
9600
2400
0.45%
-0.01%
0.45%
-0.01%
0.22%
-0.01%
-0.01%
X = Don’t care
218
434
872
1736
3480
5208
20832
SYSCLK
SYSCLK
SYSCLK / 4
SYSCLK / 4
SYSCLK / 12
SYSCLK / 12
SYSCLK / 48
SCA1-SCA0
(pre-scale
select)^†
XX
XX
01
01
00
00
10
T1M^†
1
1
0
0
0
0
0
Timer 1
Reload
Value
(hex)
0x93
0x27
0x93
0x27
0x6F
0x27
0x27
†_{SCA1-SCA0 and T1M bit definitions can be found in Section 23.1.}
Table 22.5. Timer Settings for Standard Baud Rates Using the PLL
Frequency: 100.0 MHz
Target
Baud Rate
(bps)
Baud Rate Oscilla-
% Error tor Divide
Factor
Timer
Clock
Source
230400
115200
57600
28800
14400
9600
-0.01%
0.45%
-0.01%
0.22%
-0.47%
0.45%
X = Don’t care
434
872
1736
3480
6912
10464
SYSCLK
SYSCLK / 4
SYSCLK / 4
SYSCLK / 12
SYSCLK / 48
SYSCLK / 48
SCA1-SCA0
(pre-scale
select)^†
XX
01
01
00
10
10
T1M^†
1
0
0
0
0
0
Timer 1
Reload
Value
(hex)
0x27
0x93
0x27
0x6F
0xB8
0x93
†_{SCA1-SCA0 and T1M bit definitions can be found in Section 23.1.}
Rev. 1.3
311