C8051F120 Datasheet, PDF (14/356 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
Figure 18.16. P2MDOUT: Port2 Output Mode Register ......................................... 254
Figure 18.17. P3: Port3 Data Register ................................................................... 254
Figure 18.18. P3MDOUT: Port3 Output Mode Register ......................................... 255
Figure 18.19. P4: Port4 Data Register ................................................................... 257
Figure 18.20. P4MDOUT: Port4 Output Mode Register ......................................... 257
Figure 18.21. P5: Port5 Data Register ................................................................... 258
Figure 18.22. P5MDOUT: Port5 Output Mode Register ......................................... 258
Figure 18.23. P6: Port6 Data Register ................................................................... 259
Figure 18.24. P6MDOUT: Port6 Output Mode Register ......................................... 259
Figure 18.25. P7: Port7 Data Register ................................................................... 260
Figure 18.26. P7MDOUT: Port7 Output Mode Register ......................................... 260
19. System Management Bus / I2C Bus (SMBus0) .................................................. 261
Figure 19.1. SMBus0 Block Diagram ..................................................................... 261
Figure 19.2. Typical SMBus Configuration ............................................................. 262
Figure 19.3. SMBus Transaction ............................................................................ 263
Figure 19.4. Typical Master Transmitter Sequence................................................ 264
Figure 19.5. Typical Master Receiver Sequence.................................................... 264
Figure 19.6. Typical Slave Transmitter Sequence.................................................. 265
Figure 19.7. Typical Slave Receiver Sequence...................................................... 266
Figure 19.8. SMB0CN: SMBus0 Control Register.................................................. 269
Figure 19.9. SMB0CR: SMBus0 Clock Rate Register............................................ 270
Figure 19.10. SMB0DAT: SMBus0 Data Register.................................................. 271
Figure 19.11. SMB0ADR: SMBus0 Address Register............................................ 272
Figure 19.12. SMB0STA: SMBus0 Status Register ............................................... 273
20. Enhanced Serial Peripheral Interface (SPI0)...................................................... 277
Figure 20.1. SPI Block Diagram ............................................................................. 277
Figure 20.2. Multiple-Master Mode Connection Diagram ....................................... 280
Figure 20.3. 3-Wire Single Master and 3-Wire Single Slave Mode Connection Diagram
280
Figure 20.4. 4-Wire Single Master Mode and 4-Wire Slave Mode Connection Diagram
280
Figure 20.5. Master Mode Data/Clock Timing ........................................................ 282
Figure 20.6. Slave Mode Data/Clock Timing (CKPHA = 0) .................................... 283
Figure 20.7. Slave Mode Data/Clock Timing (CKPHA = 1) .................................... 283
Figure 20.8. SPI0CFG: SPI0 Configuration Register ............................................. 284
Figure 20.9. SPI0CN: SPI0 Control Register.......................................................... 285
Figure 20.10. SPI0CKR: SPI0 Clock Rate Register ............................................... 286
Figure 20.11. SPI0DAT: SPI0 Data Register.......................................................... 287
Figure 20.12. SPI Master Timing (CKPHA = 0)...................................................... 288
Figure 20.13. SPI Master Timing (CKPHA = 1)...................................................... 288
Figure 20.14. SPI Slave Timing (CKPHA = 0)........................................................ 289
Figure 20.15. SPI Slave Timing (CKPHA = 1)........................................................ 289
21. UART0.................................................................................................................... 291
Figure 21.1. UART0 Block Diagram ....................................................................... 291
Figure 21.2. UART0 Mode 0 Timing Diagram ........................................................ 292
14
Rev. 1.3