C8051F120 Datasheet, PDF (185/356 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
Table 13.1. Reset Electrical Characteristics
-40°C to +85°C unless otherwise specified.
PARAMETER
CONDITIONS
MIN TYP MAX
/RST Output Low Voltage
I_OL = 8.5 mA, VDD = 2.7 V to 3.6 V
0.6
/RST Input High Voltage
0.7 x
VDD
/RST Input Low Voltage
0.3 x
VDD
/RST Input Leakage Current /RST = 0.0 V
50
VDD for /RST Output Valid
1.0
AV+ for /RST Output Valid
1.0
VDD POR Threshold (V_RST) Note 1
2.40 2.55 2.70
Minimum /RST Low Time to
Generate a System Reset
10
Reset Time Delay
/RST rising edge after VDD
crosses V_RST threshold
80 100 120
Missing Clock Detector Time- Time from last system clock to
out
reset initiation
100 220 500
Note 1: When operating at frequencies above 50 MHz, minimum VDD supply Voltage is 3.0 V.
UNITS
V
V
µA
V
V
V
ns
ms
µs
Rev. 1.3
187