C8051F120 Datasheet, PDF (40/356 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
3. Global DC Electrical Characteristics
Table 3.1. Global DC Electrical Characteristics (C8051F120/1/2/3 and C8051F130/1/2/3)
-40°C to +85°C, 100 MHz System Clock unless otherwise specified.
Parameter
Conditions
Min
Typ
Analog Supply Voltage (Note SYSCLK = 0 to 50 MHz
1)
SYSCLK > 50 MHz
2.7
3.0
3.0
3.3
Analog Supply Current
Internal REF, ADCs, DACs,
1.7
Comparators all active
Max Units
3.6
V
3.6
V
mA
Analog Supply Current with Internal REF, ADCs, DACs,
0.2
µA
analog sub-systems inactive Comparators all disabled, oscilla-
tor disabled
Analog-to-Digital Supply
Delta (|VDD - AV+|)
0.5
V
Digital Supply Voltage
SYSCLK = 0 to 50 MHz
SYSCLK > 50 MHz
2.7
3.0
3.6
V
3.0
3.3
3.6
V
Digital Supply Current with VDD=3.0 V, Clock=100 MHz
65
mA
CPU active
VDD=3.0 V, Clock=50 MHz
35
mA
VDD=3.0 V, Clock=1 MHz
1
mA
VDD=3.0 V, Clock=32 kHz
33
µA
Digital Supply Current with VDD=3.0 V, Clock=100 MHz
40
mA
CPU inactive (not accessing VDD=3.0 V, Clock=50 MHz
20
mA
FLASH)
VDD=3.0 V, Clock=1 MHz
0.4
mA
VDD=3.0 V, Clock=32 kHz
15
µA
Digital Supply Current (shut- Oscillator not running
down)
0.4
µA
Digital Supply RAM Data
Retention Voltage
1.5
V
SYSCLK (System Clock) VDD, AV+ = 2.7 V to 3.6 V
0
(Notes 2 and 3)
VDD, AV+ = 3.0 V to 3.6 V
0
50
MHz
100
MHz
Specified Operating Temper-
ature Range
-40
+85
°C
Note 1: Analog Supply AV+ must be greater than 1 V for VDD monitor to operate.
Note 2: SYSCLK is the internal device clock. For operational speeds in excess of 30 MHz, SYSCLK must
be derived from the Phase-Locked Loop (PLL).
Note 3: SYSCLK must be at least 32 kHz to enable debugging.
40
Rev. 1.3