C8051F120 Datasheet, PDF (42/356 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
4. Pinout and Package Definitions
Name
VDD
DGND
AV+
AGND
TMS
TCK
TDI
TDO
/RST
XTAL1
XTAL2
MONEN
Table 4.1. Pin Definitions
Pin Numbers
‘F120
‘F122
‘F124
‘F126
‘F121
‘F123
‘F125
‘F127
‘F130
‘F132
‘F131
‘F133
Type
Description
37, 24, 37, 24,
64, 90 41, 57 64, 90 41, 57
Digital Supply Voltage. Must be tied to +2.7 to
+3.6 V.
38, 25, 38, 25,
63, 89 40, 56 63, 89 40, 56
Digital Ground. Must be tied to Ground.
11, 14 6 11, 14 6
Analog Supply Voltage. Must be tied to +2.7 to
+3.6 V.
10, 13 5 10, 13 5
Analog Ground. Must be tied to Ground.
1
58
1
58 D In JTAG Test Mode Select with internal pull-up.
2
59
2
59 D In JTAG Test Clock with internal pull-up.
3
60
3
60 D In JTAG Test Data Input with internal pull-up. TDI is
latched on the rising edge of TCK.
4
61
4
61 D Out JTAG Test Data Output with internal pull-up.
Data is shifted out on TDO on the falling edge of
TCK. TDO output is a tri-state driver.
5
62
5
62 D I/O Device Reset. Open-drain output of internal
VDD monitor. Is driven low when VDD is < V_RST
and MONEN is high. An external source can ini-
tiate a system reset by driving this pin low.
26 17 26 17 A In Crystal Input. This pin is the return for the inter-
nal oscillator circuit for a crystal or ceramic reso-
nator. For a precision internal clock, connect a
crystal or ceramic resonator from XTAL1 to
XTAL2. If overdriven by an external CMOS
clock, this becomes the system clock.
27 18 27 18 A Out Crystal Output. This pin is the excitation driver
for a crystal or ceramic resonator.
28 19 28 19 D In VDD Monitor Enable. When tied high, this pin
enables the internal VDD monitor, which forces
a system reset when VDD is < V_RST. When tied
low, the internal VDD monitor is disabled.
This pin must be tied high or low.
42
Rev. 1.3