C8051F120 Datasheet, PDF (6/356 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
17.6.1.1.16-bit MOVX: EMI0CF[4:2] = ‘101’, ‘110’, or ‘111’......................... 230
17.6.1.2.8-bit MOVX without Bank Select: EMI0CF[4:2] = ‘101’ or ‘111’..... 231
17.6.1.3.8-bit MOVX with Bank Select: EMI0CF[4:2] = ‘110’....................... 232
17.6.2.Multiplexed Mode ................................................................................... 233
17.6.2.1.16-bit MOVX: EMI0CF[4:2] = ‘001’, ‘010’, or ‘011’......................... 233
17.6.2.2.8-bit MOVX without Bank Select: EMI0CF[4:2] = ‘001’ or ‘011’..... 234
17.6.2.3.8-bit MOVX with Bank Select: EMI0CF[4:2] = ‘010’....................... 235
18. Port Input/Output.................................................................................................. 239
18.1.Ports 0 through 3 and the Priority Crossbar Decoder..................................... 241
18.1.1.Crossbar Pin Assignment and Allocation ............................................... 241
18.1.2.Configuring the Output Modes of the Port Pins...................................... 242
18.1.3.Configuring Port Pins as Digital Inputs................................................... 243
18.1.4.Weak Pull-ups ........................................................................................ 243
18.1.5.Configuring Port 1 Pins as Analog Inputs .............................................. 243
18.1.6.External Memory Interface Pin Assignments ......................................... 244
18.1.7.Crossbar Pin Assignment Example........................................................ 246
18.2.Ports 4 through 7 (100-pin TQFP devices only) ............................................. 255
18.2.1.Configuring Ports which are not Pinned Out .......................................... 255
18.2.2.Configuring the Output Modes of the Port Pins...................................... 255
18.2.3.Configuring Port Pins as Digital Inputs................................................... 256
18.2.4.Weak Pull-ups ........................................................................................ 256
18.2.5.External Memory Interface ..................................................................... 256
19. System Management Bus / I2C Bus (SMBus0) .................................................. 261
19.1.Supporting Documents ................................................................................... 262
19.2.SMBus Protocol.............................................................................................. 262
19.2.1.Arbitration............................................................................................... 263
19.2.2.Clock Low Extension.............................................................................. 263
19.2.3.SCL Low Timeout................................................................................... 263
19.2.4.SCL High (SMBus Free) Timeout .......................................................... 263
19.3.SMBus Transfer Modes.................................................................................. 264
19.3.1.Master Transmitter Mode ....................................................................... 264
19.3.2.Master Receiver Mode ........................................................................... 264
19.3.3.Slave Transmitter Mode ......................................................................... 265
19.3.4.Slave Receiver Mode ............................................................................. 265
19.4.SMBus Special Function Registers ................................................................ 267
19.4.1.Control Register ..................................................................................... 267
19.4.2.Clock Rate Register ............................................................................... 270
19.4.3.Data Register ......................................................................................... 271
19.4.4.Address Register.................................................................................... 271
19.4.5.Status Register....................................................................................... 272
20. Enhanced Serial Peripheral Interface (SPI0)...................................................... 277
20.1.Signal Descriptions......................................................................................... 278
20.1.1.Master Out, Slave In (MOSI).................................................................. 278
20.1.2.Master In, Slave Out (MISO).................................................................. 278
20.1.3.Serial Clock (SCK) ................................................................................. 278
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Rev. 1.3