C8051F120 Datasheet, PDF (240/356 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
18.1. Ports 0 through 3 and the Priority Crossbar Decoder
The Priority Crossbar Decoder, or “Crossbar”, allocates and assigns Port pins on Port 0 through Port 3 to
the digital peripherals (UARTs, SMBus, PCA, Timers, etc.) on the device using a priority order. The Port
pins are allocated in order starting with P0.0 and continue through P3.7 if necessary. The digital peripher-
als are assigned Port pins in a priority order which is listed in Figure 18.3, with UART0 having the highest
priority and CNVSTR2 having the lowest priority.
18.1.1. Crossbar Pin Assignment and Allocation
The Crossbar assigns Port pins to a peripheral if the corresponding enable bits of the peripheral are set to
a logic 1 in the Crossbar configuration registers XBR0, XBR1, and XBR2, shown in Figure 18.7,
Figure 18.8, and Figure 18.9. For example, if the UART0EN bit (XBR0.2) is set to a logic 1, the TX0 and
RX0 pins will be mapped to P0.0 and P0.1 respectively.
(EMIFLE = 0; P1MDIN = 0xFF)
P0
P1
P2
P3
Crossba r Re g
PIN I/O 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
TX0
●
RX0
●
UART0EN:
SCK
●●
MISO
MOSI
●
●
●
●
S P I 0EN:
NSS
● ● NSS is not assigned to a port pin when the SPI is placed in 3-wire mode
SDA
● ●●●●●
SCL
●
●●●●●
S M B0EN:
TX1
● ●●●●●●●
RX1
●
●●●●●●●
UART1EN:
CEX 0
●
●●●●●●●●●
CEX 1
●
●●●●●●●●●
CEX 2
CEX 3
●
●●●●●●●●●
● ●●●●●●●●●
P CA0M E:
CEX 4
● ●●●●●●●●●
CEX 5
●
●●●●●●●●●
ECI
●●●●●●●●●●●●●●●●●
ECI0E:
CP0
●●●●●●●●●●●●●●●●●●
CP 0E:
CP1
●●●●●●●●●●●●●●●●●●●
CP 1E:
T0
●●●●●●●●●●●●●●●●●●●●
T0E:
/INT0
●●●●●●●●●●●●●●●●●●●●●
INT0E:
T1
●●●●●●●●●●●●●●●●●●●●●●
T1E:
/INT1
●●●●●●●●●●●●●●●●●●●●●●●
INT1E:
T2
●●●●●●●●●●●●●●●●●●●●●●●●
T2E:
T2EX
●●●●●●●●●●●●●●●●●●●●●●●●●
T 2EX E:
T4
●●●●●●●●●●●●●●●●●●●●●●●●●●
T4E:
T4EX
●●●●●●●●●●●●●●●●●●●●●●●●●●●
T 4EX E:
/SYSCLK ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ●
S YS CKE:
CNVSTR0 ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ●
CNV S T E0:
CNVSTR2 ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ●
CNV S T E2:
AIN2 Inputs/Non-muxed Addr H Muxed Addr H/Non-muxed Addr L Muxed Data/Non-muxed Data
Figure 18.3. Priority Crossbar Decode Table
242
Rev. 1.3