C8051F120 Datasheet, PDF (158/356 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
11.7.3. Interrupt Priorities
Each interrupt source can be individually programmed to one of two priority levels: low or high. A low prior-
ity interrupt service routine can be preempted by a high priority interrupt. A high priority interrupt cannot be
preempted. Each interrupt has an associated interrupt priority bit in an SFR (IP-EIP2) used to configure its
priority level. Low priority is the default. If two interrupts are recognized simultaneously, the interrupt with
the higher priority is serviced first. If both interrupts have the same priority level, a fixed priority order is
used to arbitrate, given in Table 11.4.
11.7.4. Interrupt Latency
Interrupt response time depends on the state of the CPU when the interrupt occurs. Pending interrupts are
sampled and priority decoded each system clock cycle. Therefore, the fastest possible response time is
5 system clock cycles: 1 clock cycle to detect the interrupt and 4 clock cycles to complete the LCALL to the
ISR. Additional clock cycles will be required if a cache miss occurs (see Section “16. Branch Target Cache”
on page 213 for more details). If an interrupt is pending when a RETI is executed, a single instruction is
executed before an LCALL is made to service the pending interrupt. Therefore, the maximum response
time for an interrupt (when no other interrupt is currently being serviced or the new interrupt is of greater
priority) is when the CPU is performing an RETI instruction followed by a DIV as the next instruction, and a
cache miss event also occurs. If the CPU is executing an ISR for an interrupt with equal or higher priority,
the new interrupt will not be serviced until the current ISR completes, including the RETI and following
instruction.
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