C8051F120 Datasheet, PDF (12/356 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
Figure 11.20. B: B Register .................................................................................... 157
Figure 11.21. IE: Interrupt Enable .......................................................................... 161
Figure 11.22. IP: Interrupt Priority .......................................................................... 162
Figure 11.23. EIE1: Extended Interrupt Enable 1................................................... 163
Figure 11.24. EIE2: Extended Interrupt Enable 2................................................... 164
Figure 11.25. EIP1: Extended Interrupt Priority 1................................................... 165
Figure 11.26. EIP2: Extended Interrupt Priority 2................................................... 166
Figure 11.27. PCON: Power Control ...................................................................... 168
12. Multiply And Accumulate (MAC0) ....................................................................... 169
Figure 12.1. MAC0 Block Diagram ......................................................................... 169
Figure 12.2. Integer Mode Data Representation .................................................... 170
Figure 12.3. Fractional Mode Data Representation................................................ 170
Figure 12.4. MAC0 Pipeline.................................................................................... 171
Figure 12.5. Multiply and Accumulate Example ..................................................... 172
Figure 12.6. Multiply Only Example........................................................................ 173
Figure 12.7. MAC0 Accumulator Shift Example ..................................................... 173
Figure 12.8. MAC0CF: MAC0 Configuration Register............................................ 174
Figure 12.9. MAC0STA: MAC0 Status Register..................................................... 175
Figure 12.10. MAC0AH: MAC0 A High Byte Register ............................................ 175
Figure 12.11. MAC0AL: MAC0 A Low Byte Register ............................................. 176
Figure 12.12. MAC0BH: MAC0 B High Byte Register ............................................ 176
Figure 12.13. MAC0BL: MAC0 B Low Byte Register ............................................. 176
Figure 12.14. MAC0ACC3: MAC0 Accumulator Byte 3 Register ........................... 177
Figure 12.15. MAC0ACC2: MAC0 Accumulator Byte 2 Register ........................... 177
Figure 12.16. MAC0ACC1: MAC0 Accumulator Byte 1 Register ........................... 177
Figure 12.17. MAC0ACC0: MAC0 Accumulator Byte 0 Register ........................... 178
Figure 12.18. MAC0OVR: MAC0 Accumulator Overflow Register ......................... 178
Figure 12.19. MAC0RNDH: MAC0 Rounding Register High Byte.......................... 178
Figure 12.20. MAC0RNDL: MAC0 Rounding Register Low Byte ........................... 179
13. Reset Sources....................................................................................................... 181
Figure 13.1. Reset Sources.................................................................................... 181
Figure 13.2. Reset Timing ...................................................................................... 182
Figure 13.3. WDTCN: Watchdog Timer Control Register....................................... 185
Figure 13.4. RSTSRC: Reset Source Register ...................................................... 186
14. Oscillators ............................................................................................................. 189
Figure 14.1. Oscillator Diagram.............................................................................. 189
Figure 14.2. OSCICL: Internal Oscillator Calibration Register ............................... 190
Figure 14.3. OSCICN: Internal Oscillator Control Register .................................... 190
Figure 14.4. CLKSEL: System Clock Selection Register ....................................... 192
Figure 14.5. OSCXCN: External Oscillator Control Register.................................. 193
Figure 14.6. PLL Block Diagram............................................................................. 195
Figure 14.7. PLL0CN: PLL Control Register .......................................................... 197
Figure 14.8. PLL0DIV: PLL Pre-divider Register.................................................... 197
Figure 14.9. PLL0MUL: PLL Clock Scaler Register ............................................... 198
Figure 14.10. PLL0FLT: PLL Filter Register........................................................... 198
12
Rev. 1.3