C8051F120 Datasheet, PDF (313/356 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
23. Timers
Each MCU includes 5 counter/timers: Timer 0 and Timer 1 are 16-bit counter/timers compatible with those
found in the standard 8051. Timer 2, Timer 3, and Timer 4 are 16-bit auto-reload and capture counter/tim-
ers for use with the ADCs, DACs, square-wave generation, or for general-purpose use. These timers can
be used to measure time intervals, count external events and generate periodic interrupt requests. Timer 0
and Timer 1 are nearly identical and have four primary modes of operation. Timer 3 offers 16-bit auto-
reload and capture. Timers 2 and 4 are identical, and offer not only 16-bit auto-reload and capture, but
have the ability to produce a 50% duty-cycle square-wave (toggle output) at an external port pin.
Timer 0 and Timer 1 Modes:
13-bit counter/timer
16-bit counter/timer
8-bit counter/timer with auto-reload
Two 8-bit counter/timers (Timer 0 only)
Timer 2, 3 and 4 Modes:
16-bit counter/timer with auto-reload
16-bit counter/timer with capture
Toggle Output (Timer 2 and 4 only)
Timers 0 and 1 may be clocked by one of five sources, determined by the Timer Mode Select bits (T1M-
T0M) and the Clock Scale bits (SCA1-SCA0). The Clock Scale bits define a pre-scaled clock by which
Timer 0 and/or Timer 1 may be clocked (See Figure 23.6 for pre-scaled clock selection). Timers 0 and 1
can be configured to use either the pre-scaled clock signal or the system clock directly. Timers 2, 3, and 4
may be clocked by the system clock, the system clock divided by 12, or the external oscillator clock source
divided by 8.
Timer 0 and Timer 1 may also be operated as counters. When functioning as a counter, a counter/timer
register is incremented on each high-to-low transition at the selected input pin. Events with a frequency of
up to one-fourth the system clock's frequency can be counted. The input signal need not be periodic, but it
should be held at a given logic level for at least two full system clock cycles to ensure the level is properly
sampled.
23.1. Timer 0 and Timer 1
Each timer is implemented as a 16-bit register accessed as two separate 8-bit SFRs: a low byte (TL0 or
TL1) and a high byte (TH0 or TH1). The Counter/Timer Control register (TCON) is used to enable Timer 0
and Timer 1 as well as indicate their status. Timer 0 interrupts can be enabled by setting the ET0 bit in the
IE register (Section “11.7.5. Interrupt Register Descriptions” on page 159); Timer 1 interrupts can be
enabled by setting the ET1 bit in the IE register (Section 11.7.5). Both counter/timers operate in one of four
primary modes selected by setting the Mode Select bits T1M1-T0M0 in the Counter/Timer Mode register
(TMOD). Both timers can be configured independently.
23.1.1. Mode 0: 13-bit Counter/Timer
Timer 0 and Timer 1 operate as 13-bit counter/timers in Mode 0. The following describes the configuration
and operation of Timer 0. However, both timers operate identically, and Timer 1 is configured in the same
manner as described for Timer 0.
The TH0 register holds the eight MSBs of the 13-bit counter/timer. TL0 holds the five LSBs in bit positions
TL0.4-TL0.0. The three upper bits of TL0 (TL0.7-TL0.5) are indeterminate and should be masked out or
ignored when reading the TL0 register. As the 13-bit timer register increments and overflows from 0x1FFF
(all ones) to 0x0000, the timer overflow flag TF0 (TCON.5) is set and an interrupt will occur if Timer 0 inter-
rupts are enabled.
Rev. 1.3
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