C8051F120 Datasheet, PDF (324/356 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
23.2.3. Auto-Reload Mode
In Auto-Reload Mode, the counter/timer can be configured to count up or down and cause an interrupt/flag
to occur upon an overflow/underflow event. When counting up, the counter/timer will set its overflow/under-
flow flag (TFn) and cause an interrupt (if enabled) upon overflow/underflow, and the values in the Reload/
Capture Registers (RCAPnH and RCAPnL) are loaded into the timer and the timer is restarted. When the
Timer External Enable Bit (EXENn) bit is set to ‘1’ and the Decrement Enable Bit (DCENn) is ‘0’, a falling
edge (‘1’-to-‘0’ transition) on the TnEX pin will cause a timer reload. Note that timer overflows will also
cause auto-reloads. When DCENn is set to ‘1’, the state of the TnEX pin controls whether the counter/timer
counts up (increments) or down (decrements), and will not cause an auto-reload or interrupt event (Timer 3
shares the T2EX pin with Timer 2). See Section 23.2.1 for information concerning configuration of a timer
to count down.
When counting down, the counter/timer will set its overflow/underflow flag (TFn) and cause an interrupt (if
enabled) when the value in the TMRnH and TMRnL registers matches the 16-bit value in the Reload/Cap-
ture Registers (RCAPnH and RCAPnL). This is considered an underflow event, and will cause the timer to
load the value 0xFFFF. The timer is automatically restarted when an underflow occurs.
Counter/Timer with Auto-Reload mode is selected by clearing the CP/RLn bit. Setting TRn to logic 1
enables and starts the timer.
In Auto-Reload Mode, the External Flag (EXFn) toggles upon every overflow or underflow and does not
cause an interrupt. The EXFn flag can be used as the most significant bit (MSB) of a 17-bit counter.
.
2
SYSCLK
12
TMRnCF
TTTTD
n nOnC
MMGO E
1 0 nEN
Toggle Logic
0
0xFF
0xFF
1
Tn
(Port Pin)
External Clock
8
Tn
Crossbar
0
1
TRn
TCLK ^TMRnL
OVF
TMRnH
CP/RLn
C/Tn
TRn
EXENn
EXENn
TnE
Crossbar
X
SMBus
(Timer 3 Only)
Reload _{RCAPnL RCAPnH}
EXFn
TFn
Figure 23.12. T2, 3, and 4 Auto-reload Mode Block Diagram
Interrupt
23.2.4. Toggle Output Mode (Timer 2 and Timer 4 Only)
Timers 2 and 4 have the capability to toggle the state of their respective output port pins (T2 or T4) to pro-
duce a 50% duty cycle waveform output. The port pin state will change upon the overflow or underflow of
the respective timer (depending on whether the timer is counting up or down). The toggle frequency is
determined by the clock source of the timer and the values loaded into RCAPnH and RCAPnL. When
counting DOWN, the auto-reload value for the timer is 0xFFFF, and underflow will occur when the value in
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Rev. 1.3