C8051F120 Datasheet, PDF (328/356 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
Figure 23.15. RCAPnL: Timer 2, 3, and 4 Capture Register Low Byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR
Address:
RCAP2L:
0xCA;
RCAP3L:
0xCA;
RCAP4L:
0xCA
SFR Page: RCAP2L: page 0; RCAP3L: page 1; RCAP4L: page 2
Bits 7-0:
RCAP2, 3, and 4L: Timer 2, 3, and 4 Capture Register Low Byte.
The RCAP2, 3, and 4L register captures the low byte of Timer 2, 3, and 4 when Timer 2, 3,
and 4 is configured in capture mode. When Timer 2, 3, and 4 is configured in auto-reload
mode, it holds the low byte of the reload value.
Figure 23.16. RCAPnH: Timer 2, 3, and 4 Capture Register High Byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR
Address:
RCAP2H:
0xCB;
RCAP3H:
0xCB;
RCAP4H:
0xCB
SFR Page: RCAP2H: page 0; RCAP3H: page 1; RCAP4H: page 2
Bits 7-0: RCAP2, 3, and 4H: Timer 2, 3, and 4 Capture Register High Byte.
The RCAP2, 3, and 4H register captures the high byte of Timer 2, 3, and 4 when Timer 2, 3,
and 4 is configured in capture mode. When Timer 2, 3, and 4 is configured in auto-reload
mode, it holds the high byte of the reload value.
Figure 23.17. TMRnL: Timer 2, 3, and 4 Low Byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR
Address:
TMR2L:
0xCC;
TMR3L:
0xCC;
TMR4L:
0xCC
SFR Page: TMR2L: page 0; TMR3L: page 1; TMR4L: page 2
Bits 7-0: TL2, 3, and 4: Timer 2, 3, and 4 Low Byte.
The TL2, 3, and 4 register contains the low byte of the 16-bit Timer 2, 3, and 4
328
Rev. 1.3