C8051F120 Datasheet, PDF (234/356 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
Table 17.1. AC Parameters for External Memory Interface†
Parameter
Description
Min
T_ACS
Address / Control Setup Time
0
T_ACW
Address / Control Pulse Width
1*T_SYSCLK
T_ACH
Address / Control Hold Time
0
T_ALEH
Address Latch Enable High Time
1*T_SYSCLK
T_ALEL
Address Latch Enable Low Time
1*T_SYSCLK
T_WDS
Write Data Setup Time
1*T_SYSCLK
T_WDH
Write Data Hold Time
0
T_RDS
Read Data Setup Time
20
T_RDH
Read Data Hold Time
0
†_{TSYSCLK is equal to one period of the device system clock (SYSCLK).}
Max
3*T_SYSCLK
16*T_SYSCLK
3*T_SYSCLK
4*T_SYSCLK
4*T_SYSCLK
19*T_SYSCLK
3*T_SYSCLK
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
236
Rev. 1.3