C8051F120 Datasheet, PDF (117/356 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
9.2. Reference Configuration on the C8051F121/3/5/7
On the C8051F121/3/5/7 devices, the REF0CN register also allows selection of the voltage reference
source for ADC0 and ADC2, as shown in Figure 9.4. Bits AD0VRS and AD2VRS in the REF0CN register
select the ADC0 and ADC2 voltage reference sources, respectively. The VREFA pin provides a voltage
reference input for ADC0 and ADC2, which can be connected to an external precision reference or the
internal voltage reference. ADC0 may also reference the DAC0 output internally, and ADC2 may reference
the analog power supply voltage, via the VREF multiplexers shown in Figure 9.3.
REF0CN
External
Voltage
Reference
Circuit
VDD
R1
DGND
VREFA
AV+
1
0
0
ADC2
Ref
ADC0
Ref
1
DAC0
Ref
DAC1
BIASE
+
4.7µF
VREF
0.1µF
Recommended Bypass
Capacitors
x2
REFBE
EN
1.2V
Band-Gap
Bias to
ADCs,
DACs
Figure 9.3. Voltage Reference Functional Block Diagram (C8051F121/3/5/7)
Rev. 1.3
117