C8051F120 Datasheet, PDF (310/356 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
Table 22.2. Timer Settings for Standard Baud Rates Using an External Oscillator
Frequency: 25.0 MHz
Target Baud Rate Oscilla-
Baud Rate % Error tor Divide
Timer
Clock
SCA1-SCA0
(pre-scale
T1M^{† Timer 1}
Reload
(bps)
Factor
Source
select)^†
Value
(hex)
230400
-0.47%
108
SYSCLK
XX
1
0xCA
115200
0.45%
218
SYSCLK
XX
1
0x93
57600
-0.01%
434
SYSCLK
XX
1
0x27
28800
0.45%
872 SYSCLK / 4
01
0
0x93
14400
-0.01%
1736 SYSCLK / 4
01
0
0x27
9600
0.15%
2608 EXTCLK / 8
11
0
0x5D
2400
0.45%
10464 SYSCLK / 48
10
0
0x93
1200
-0.01%
20832 SYSCLK / 48
10
0
0x27
57600
-0.47%
432 EXTCLK / 8
11
0
0xE5
28800
-0.47%
864 EXTCLK / 8
11
0
0xCA
14400
0.45%
1744 EXTCLK / 8
11
0
0x93
9600
0.15%
2608 EXTCLK / 8
11
0
0x5D
X = Don’t care
†_{SCA1-SCA0 and T1M bit definitions can be found in Section 23.1.}
Table 22.3. Timer Settings for Standard Baud Rates Using an External Oscillator
Frequency: 22.1184 MHz
Target Baud Rate Oscilla-
Baud Rate % Error tor Divide
(bps)
Factor
Timer
Clock
Source
230400
115200
57600
28800
14400
9600
2400
1200
230400
115200
57600
28800
14400
9600
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
X = Don’t care
96
192
384
768
1536
2304
9216
18432
96
192
384
768
1536
2304
SYSCLK
SYSCLK
SYSCLK
SYSCLK / 12
SYSCLK / 12
SYSCLK / 12
SYSCLK / 48
SYSCLK / 48
EXTCLK / 8
EXTCLK / 8
EXTCLK / 8
EXTCLK / 8
EXTCLK / 8
EXTCLK / 8
SCA1-SCA0
(pre-scale
select)^†
XX
XX
XX
00
00
00
10
10
11
11
11
11
11
11
T1M^†
1
1
1
0
0
0
0
0
0
0
0
0
0
0
Timer 1
Reload
Value
(hex)
0xD0
0xA0
0x40
0xE0
0xC0
0xA0
0xA0
0x40
0xFA
0xF4
0xE8
0xD0
0xA0
0x70
†_{SCA1-SCA0 and T1M bit definitions can be found in Section 23.1.}
310
Rev. 1.3