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M16C29 Datasheet, PDF (98/499 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/Tiny SERIES
M16C/29 Group
9. Interrupts
9.2.2 Relocatable Vector Tables
The 256 bytes beginning with the start address set in the INTB register comprise a reloacatable vector
table area. Table 9.2 lists the relocatable vector tables. Setting an even address in the INTB register
results in the interrupt sequence being executed faster than in the case of odd addresses.
Table 9.2 Relocatable Vector Tables
Interrupt source
Vector address (1)
Address (L) to address (H)
Software interrupt
number
Reference
BRK instruction (2)
+0 to +3 (0000 16 to 000316)
0
CAN0 wakeup (3)
+4 to +7 (0004 16 to 000716)
1
CAN0 receive completion
+8 to +11 (0008 16 to 000B16)
2
CAN0 transmit completion
+12 to +15 (000C 16 to 000F16)
3
INT3
+16 to +19 (0010 16 to 001316)
4
IC/OC interrupt 0
+20 to +23 (0014 16 to 001716)
5
IC/OC interrupt 1, I 2C bus interface (4)
+24 to +27 (0018 16 to 001B16)
6
IC/OC base timer, S CL/SDA(4)
+28 to +31 (001C 16 to 001F16)
7
SI/O4, INT5(5)
+32 to +35 (0020 16 to 002316)
8
SI/O3, INT4(5)
+36 to +39 (0024 16 to 002716)
9
UART 2 bus collision detection (6)
+40 to +43 (0028 16 to 002B16)
10
DMA0
+44 to +47 (002C 16 to 002F16)
11
DMA1
+48 to +51 (0030 16 to 003316)
12
CAN0 state, error
+52 to +55 (0034 16 to 003716)
13
A/D, Key input interrupt (7)
+56 to +59 (0038 16 to 003B16)
14
UART2 transmit, NACK2 (8)
UART2 receive, ACK2 (8)
UART0 transmit
UART0 receive
UART1 transmit
UART1 receive
Timer A0
Timer A1
+60 to +63 (003C 16 to 003F16)
15
+64 to +67 (0040 16 to 004316)
16
+68 to +71 (0044 16 to 004716)
17
+72 to +75 (0048 16 to 004B16)
18
+76 to +79 (004C 16 to 004F16)
19
+80 to +83 (0050 16 to 005316)
20
+84 to +87 (0054 16 to 005716)
21
+88 to +91 (0058 16 to 005B16)
22
M16C/60, M16C/20
series software
manual
CAN module
INT interrupt
Timer S
Timer S
Multi-Master I2C bus
interface
INT interrupt
Serial I/O
Serial I/O
DMAC
CAN module
A/D convertor,
Key input interrupt
Serial I/O
Timer A2
Timer A3
Timer A4
Timer B0
Timer B1
Timer B2
INT0
INT1
INT2
+92 to +95 (005C 16 to 005F16)
23
+96 to +99 (0060 16 to 006316)
24
+100 to +103 (0064 16 to 006716)
25
+104 to +107 (0068 16 to 006B16)
26
+108 to +111 (006C 16 to 006F16)
27
+112 to +115 (0070 16 to 007316)
28
+116 to +119 (0074 16 to 007716)
29
+120 to +123 (0078 16 to 007B16)
30
+124 to +127 (007C 16 to 007F16)
31
Timer
INT interrupt
Software interrupt (2)
+128 to +131 (0080 16 to 008316)
32
to
to
+252 to +255 (00FC 16 to 00FF16)
63
M16C/60, M16C/20
series software
manual
NOTES:
1. Address relative to address in INTB.
2. These interrupts cannot be disabled using the I flag.
3. Set the IFSR22 bit in the IFSR register to 0.
4. Use bits IFSR26 and IFSR27 in the IFSR2A register to select.
5. Use bits IFSR6 and IFSR7 in the IFSR register to select.
6. Bus collision detection: In IEBus mode, this bus collision detection constitutes the cause of an interrupt. In I2C bus
mode, however, a start condition or a stop condition detection constitutes the cause of an interrupt.
7. Use the IFSR21 bit in the IFSR2A register to select.
8. During I2C bus mode, NACK and ACK interrupts comprise the interrupt source.
Rev. 1.12 Mar.30, 2007
REJ09B0101-0112
page 74 of 458