M16C29 Datasheet, PDF (255/499 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/Tiny SERIES

M16C/29 Group
15. A/D Converter
A/D Control Register 0 ⁽¹⁾
b7 b6 b5 b4 b3 b2 b1 b0
01
Symbol
ADCON0
Address
03D616
After Reset
00000XXX 2
Bit Symbol
Bit Name
Function
RW
b2 b1 b0
CH0
0 0 0: Select AN0
RW
0 0 1: Select AN1
0 1 0: Select AN2
CH1
Analog input pin select
0 1 1: Select AN3
RW
bit^{(2, 3)}
1 0 0: Select AN4
1 0 1: Select AN5
CH2
1 1 0: Select AN6
RW
1 1 1: Select AN7
MD0
MD1
A/D operation mode
select bit 0 ⁽³⁾
b4 b3
0 1: Repeat mode
RW
RW
TRG
Trigger select bit
0: Software trigger
1: Hardware trigger (ADTRG trigger)
RW
ADST
A/D conversion start flag
0: A/D conversion disabled
1: A/D conversion started
RW
CKS0 Frequency select bit 0
See Table 15.2
RW
NOTES:
1. If the ADCON0 register is rewritten during A/D conversion, the conversion result will be undefined.
2. AN00 to AN07, AN20 to AN27, and AN30 to AN32 can be used in the same way as AN0 to AN7. Use bits ADGSEL1
and ADGSEL 0 in the ADCON2 register to select the desired pin.
3. After rewriting bits MD1 and MD0, set bits CH2 to CH0 over again using an another instruction.
A/D Control Register 1 ⁽¹⁾
b7 b6 b5 b4 b3 b2 b1 b0
1
0
Symbol
ADCON1
Address
03D716
After Reset
0016
Bit Symbol
Bit Name
Function
RW
SCAN0
RW
A/D sweep pin select bit Invalid in repeat mode
SCAN1
RW
A/D operation mode
MD2
select bit 1
0: Other than repeat sweep mode 1
RW
BITS
8/10-bit mode select bit
0: 8-bit mode
1: 10-bit mode
RW
CKS1 Frequency select bit 1
See Table 15.2
RW
VCUT Vref connect bit ⁽²⁾
1: Vref connected
RW
(b7-b6)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0
NOTES:
1. If the ADCON1 register is rewritten during A/D conversion, the conversion result will be undefined.
2. If the VCUT bit is reset from 0 (Vref unconnected) to 1 (Vref connected), wait for 1 µs or more before starting A/D
conversion.
A/D Control Register 2⁽¹⁾
b7 b6 b5 b4 b3 b2 b1 b0
00
Symbol
ADCON2
Address
03D416
After Reset
0016
Bit Symbol
Bit Name
Function
RW
SMP
A/D conversion method
select bit
0: Without sample and hold
1: With sample and hold
RW
b2 b1
ADGSEL0
0 0: Select port P10 group
RW
A/D input group select bit _{0 1: Select port P9 group}
ADGSEL1
1 0: Select port P0 group
1 1: Select port P1/P9 group
RW
(b3)
Reserved bit
Set to 0
RW
CKS2 Frequency select bit 2
See Table 15.2
RW
TRG1 Trigger select bit
Set to 0 in one-shot mode
RW
(b7-b6)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0
NOTE:
1. If the ADCON2 register is rewritten during A/D conversion, the conversion result will be undefined.
Figure 15.9 ADCON0 to ADCON2 Registers in Repeat Mode
Rev. 1.12 Mar.30, 2007 ^{page 231} of 458
REJ09B0101-0112