M16C29 Datasheet, PDF (72/499 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/Tiny SERIES

M16C/29 Group
7. Clock Generation Circuit
Sub-clock
generating circuit
XCIN
XCOUT
CM04
CM21
CM10=1(stop mode)
WAIT instruction
SQ
R
XIN
XOUT
Main
clock
Main clock
CM05 ^{generating circuit}
SQ
R
RESET
Software reset
NMI
Interrupt request level judgment output
CM00, CM01, CM02, CM04, CM05, CM06, CM07: Bits in the CM0 register
CM10, CM11, CM16, CM17: Bits in the CM1 register
PCLK0, PCLK1, PCLK5: Bits in the PCLKR register
CM21, CM27: Bits in the CM2 register
CCLK2-CCLK0=0002
CCLK2-CCLK0=0012
CCLK2-CCLK0=0102
fCAN
CCLK2-CCLK0=0112
CCLK2-CCLK0=1002
CAN module
system clock
divider
I/O ports
Sub-clock
fC
Variable
on-chip
oscillator
On-chip
oscillator
clock
Oscillation
stop, re-
oscillation
detection
circuit
PLL
frequency
synthesizer
PLL
1 ^clock
0
CM11
CM21=1
CM21=0
CM02
PCLK5=0,CM01-CM00=002
PCLK5=0,CM01-CM00=012
PCLK5=1,
CM01-CM00=002
PCLK5=0,
CM01-CM00=102
1/32
fC32
f1 PCLK0=1
f2
PCLK0=0
f8
CLKOUT
PCLK5=0,
CM01-CM00=112
f32
fAD
f1SIO
f2SIO
PCLK1=1
PCLK1=0
f8SIO
eb c
a
ed
f32SIO
CM07=0
fC
CM07=1
D4INT clock
CPU clock
BCLK
e
b
c
a
1/2
1/2
1/2
1/2
1/2
1/32
1/2
1/4
1/8
1/16
CM06=1
CM06=0
CM17, CM16=102
CM06=0
CM17, CM16=112
d
CM06=0
CM17, CM16=012
CM06=0
CM17, CM16=002
Details of divider
Oscillation stop, re-oscillation detection circuit
Main
clock
Pulse generation
circuit for clock
edge detection
and charge,
discharge control
Charge,
discharge
circuit
CM27=0
CM27=1
Reset
generating
circuit
Oscillation stop
detection reset
Oscillation stop,
re-oscillation
detection interrupt
generating circuit
Oscillation stop,
re-oscillation
detection signal
CM21 switch signal
Variable On-chip Oscillator
f1(ROC)
ROCR1, ROCR0=002
f2(ROC)
ROCR1,ROCR0=012
f3(ROC)
ROCR1, ROCR0=112
1/2
1/2
1/2
1/2
1/4
1/8
ROCR3, ROCR2=112
ROCR3, ROCR2=102
ROCR3, ROCR2=012
On-chip
oscillator
clock
PLL frequency synthesizer
Main clock
Programmable
counter
Phase
comparator
Charge
pump
Voltage
1/2
control
oscillator
(VCO)
Internal low-
pass filter
PLL clock
Figure 7.1 Clock Generation Circuit
Rev. 1.12 Mar.30, 2007
REJ09B0101-0112
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