M16C29 Datasheet, PDF (190/499 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/Tiny SERIES

M16C/29 Group
13. Timer S
13.5.3 Set/Reset Waveform Output (SR Waveform Output) Mode
Output signal level of the OUTC1j pin becomes high ("H") when the INV bit in the G1POCRi (i=0 to 7) is
set to 0 (output is not reversed) and the base timer value matches the G1POj register value (j=0, 2, 4, 6).
The "H" signal switches to a low-level ("L") signal when the base timer value matches the G1POk (k=j+1)
register value. Table 13.10 lists specifications of SR waveform mode. Figure 13.24 shows an example of
the SR waveform mode operation.
Table 13.10 SR Waveform Output Mode Specifications
Item
Specification
Output waveform
• Free-running operation
(the RST1, RTS2, and RST4 bits of the G1BCR1 and G1BCR0 registers are set
to 0 (no reset))
Cycle
: ⁶⁵⁵³⁶
fBT1
Inverse level width⁽¹⁾ : ^n-m
fBT1
• The base timer is cleared to 000016 by matching the base timer with either
following register
(a) G1PO0 register (enabled by setting RST1 bit to 1, and bits RST4 and RST2 to 0)⁽²⁾, or
(b) G1BTRR register (enabled by setting RST4 bit to 1, and bits RST2 and RST1 to 0)
Cycle
:
Inverse level width⁽¹⁾ :
p+2
fBT1
n-m
fBT1
m : setting value of the G1POj register (j=0, 2, 4, 6 )
n : setting value of the G1POk register (k=j+1)
p : setting value of the G1PO0 register or G1BTRR register
value range of m, n, p: 000116 to FFFD16
Waveform output start condition Bits IFEj and IFEk in the G1FE register is set to 1 (channel j function enabled)
Waveform output stop condition Bits IFEj and IFEk are set to 0 (channel j function disabled)
Interrupt request
OUTC1j pin ⁽³⁾
The G1IRj bit in the G1IR register is set to 1 when the base timer value
matches the G1POj register value.
The G1IRk bit in the interrupt request register is set to 1 when the base timer
value matches the G1POk register value (See Figure 13.24)
Pulse signal output pin
Selectable function
• Default value set function : Set starting waveform output level
• Inverse output function: Waveform output signal is inversed and provided
from the OUTC1j pin
NOTES:
1. The odd channel's waveform generating register must have greater value than the even channel's.
2. When the G1PO0 register resets the base timer, the channel 0 and channel 1 SR waveform generating functions
are not available.
3. Pins OUTC10, OUTC12, OUTC14, OUTC16.
Rev. 1.12 Mar.30, 2007 ^{page 166} of 458
REJ09B0101-0112