M16C29 Datasheet, PDF (282/499 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/Tiny SERIES

M16C/29 Group
16. MULTI-MASTER I²C bus INTERFACE
I²C0 Data Shift Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
S00
Address
02E016
After Reset
XX16
Function
RW
Transmit/receive data are stored.
In master transmit mode, the start condition/stop condition are triggered by writing data
to the register (refer to 16.9 START Condition Generation Method and 16.11 STOP
Condition Generation Method). Start transmitting/receiving data while synchronizing
with SCL
RW⁽¹⁾
NOTE:
1. Write is enabled only when the ES0 bit in the S1D0 register is 1 (I²C bus interface is enabled). Write the transmit data after
the receive data is read because the S00 register is used to store both the transmit and receive data. When the S00 register
is set, bits BC2 to BC0 in the S1D0 register are set to 0002, while bits LRB, AAS, and AL in the S10 register are set to 0
respectively.
I²C0 Clock Control Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
S20
Address
02E416
After Reset
0016
Bit Symbol
Bit Name
Function
RW
CCR0 ^{SCL Frequency Control Bits See Table 16.3}
RW
CCR1
RW
CCR2
RW
CCR3
RW
CCR4
FAST
MODE
ACKBIT
SCL Mode Specification Bit
ACK Bit
ACK-CLK ACK Clock Bit
RW
0: Standard clock mode
1: High-speed clock mode
RW
0: ACK is returned
RW
1: ACK is not returned
0: No ACK clock
1: With ACK clock
RW
Figure 16.3 S00 and S20 Registers
Rev. 1.12 Mar.30, 2007 ^{page 258} of 458
REJ09B0101-0112