M16C29 Datasheet, PDF (263/499 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/Tiny SERIES

M16C/29 Group
15. A/D Converter
A/D Control Register 0 ⁽¹⁾
b7 b6 b5 b4 b3 b2 b1 b0
11
Symbol
ADCON0
Address
03D616
After Reset
00000XXX 2
Bit Symbol
CH0
Bit Name
Function
RW
RW
CH1
Analog input pin select bit Invalid in repeat sweep mode 0
RW
CH2
RW
MD0
MD1
A/D operation mode
select bit 0
b4 b3
RW
1 0: Single sweep mode or
simultaneous sample sweep mode
RW
TRG
Trigger select bit
See Table 15.9
RW
ADST
A/D conversion start flag
0: A/D conversion disabled
1: A/D conversion started
RW
CKS0 Frequency select bit 0
See Table 15.2
RW
NOTE:
1. If the ADCON0 register is rewritten during A/D conversion, the conversion result will be undefined.
A/D Control Register 1⁽¹⁾
b7 b6 b5 b4 b3 b2 b1 b0
1
0
Symbol
ADCON1
Address
03D716
After Reset
0016
Bit Symbol
Bit Name
Function
RW
When simultaneous sample sweep mode
SCAN0
is selected,
b1 b0
RW
A/D sweep pin select bit ^{(2) 0 0: AN0 to AN1 (2 pins)}
0 1: AN0 to AN3 (4 pins)
SCAN1
1 0: AN0 to AN5 (6 pins)
RW
1 1: AN0 to AN7 (8 pins)
MD2
A/D operation mode
select bit 1
0: Other than repeat sweep mode 1
RW
BITS
8/10-bit mode select bit
0: 8-bit mode
1: 10-bit mode
RW
CKS1 Frequency select bit 1
See Table 15.2
RW
VCUT Vref connect Bit ⁽³⁾
1: Vref connected
RW
(b7-b6)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0
NOTES:
1. If the ADCON1 register is rewritten during A/D conversion, the conversion result will be undefined.
2. AN00 to AN07, AN20 to AN27, and AN30 to AN32 can be used in the same way as AN0 to AN7. Use bits ADGSEL1
and ADGSEL 0 in the ADCON2 register to select the desired pin.
3. If the VCUT bit is reset from 0 (Vref unconnected) to 1 (Vref connected), wait for 1 µs or more before starting A/D
conversion.
A/D Control Register 2⁽¹⁾
b7 b6 b5 b4 b3 b2 b1 b0
0
1
Symbol
ADCON2
Address
03D416
After Reset
0016
Bit Symbol
Bit Name
Function
RW
SMP
A/D conversion method
select bit
Set to 1 in simultaneous sample sweep
mode
RW
ADGSEL0
b2 b1
0 0: Select port P10 group
RW
A/D input group select bit 0 1: Select port P9 group
ADGSEL1
1 0: Select port P0 group
1 1: Select port P1/P9 group
RW
(b3)
Reserved bit
Set to 0
RW
CKS2 Frequency select bit 2
See Table 15.2
RW
TRG1 Trigger select bit
See Table 15.9
RW
(b7-b6)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0
NOTE:
1. If the ADCON2 register is rewritten during A/D conversion, the conversion result will be undefined.
Figure 15.17 ADCON0 to ADCON2 Registers in Simultaneous Sample Sweep Mode
Rev. 1.12 Mar.30, 2007 ^{page 239} of 458
REJ09B0101-0112