M16C29 Datasheet, PDF (121/499 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/Tiny SERIES

M16C/29 Group
11. DMAC
(1) When the transfer unit is 8 or 16 bits and the source of transfer is an even address
CPU clock
Address
bus
RD signal
WR signal
Data
bus
CPU use
CPU use
Source
Destination
Dummy
cycle
CPU use
Source
Destination
Dummy
cycle
CPU use
(2) When the transfer unit is 16 bits and the source address of transfer is an odd address.
CPU clock
Address
bus
RD signal
WR signal
Data
bus
CPU use
CPU use
Source Source + 1
Destination
Dummy
cycle
CPU use
Source Source + 1
Destination
Dummy
cycle
CPU use
(3) When the source read cycle under condition (1) has one wait state inserted
CPU clock
Address
bus
CPU use
Source
Destination
Dummy
cycle
CPU use
RD signal
WR signal
Data
bus
CPU use
Source
Destination
Dummy
cycle
CPU use
(4) When the source read cycle under condition (2) has one wait state inserted
CPU clock
Address
bus
RD signal
WR signal
Data
bus
CPU use
CPU use
Source
Source + 1
Destination
Dummy
cycle
CPU use
Source
Source + 1
Destination
Dummy
cycle
CPU use
NOTE:
1. The same timing changes occur with the respective conditions at the destination as at the source.
Figure 11.5 Transfer Cycles for Source Read
Rev. 1.12 Mar.30, 2007
REJ09B0101-0112
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