M16C29 Datasheet, PDF (209/499 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/Tiny SERIES

M16C/29 Group
14. Serial I/O
14.1.1.2 CLK Polarity Select Function
Use the CKPOL bit in the UiC0 register (i=0 to 2) to select the transfer clock polarity. Figure 14.11
shows the polarity of the transfer clock.
(1) When the CKPOL bit in the UiC0 register is set to 0 (transmit data output at the falling edge
and the receive data taken in at the rising edge of the transfer clock)
CLKi
(2)
TXDi
D0 D1 D2 D3 D4 D5 D6 D7
RXDi
D0
D1
D2
D3
D4
D5
D6
D7
(2) When the CKPOL bit in the UiC0 register is set to 1 (transmit data output at the rising
edge and the receive data taken in at the falling edge of the transfer clock)
CLKi
(3)
TXDi
D0 D1 D2 D3 D4 D5 D6 D7
RXDi
D0
D1
D2
D3
D4
D5
D6
D7
i = 0 to 2
NOTES:
1. This applies to the case where the UFORM bit in the UiC0 register is set to 0 (LSB first) and the
UiLCH bit in the UiC1 register is set to 0 (no reverse).
2. When not transferring, the CLKi pin outputs a high signal.
Figure 14.11 Polarity of transfer clock
14.1.1.3 LSB First/MSB First Select Function
Use the UFORM bit in the UiC0 register (i=0 to 2) to select the transfer format. Figure 14.12 shows
the transfer format.
(1) When the UFORM bit in the UiC0 register 0 (LSB first)
CLKi
TXDi
D0 D1 D2 D3 D4 D5 D6 D7
RXDi
D0 D1 D2 D3 D4 D5 D6 D7
(2) When the UFORM bit in the UiC0 register is set to 1 (MSB first)
CLKi
TXDi
D7 D6 D5 D4 D3 D2 D1 D0
RXDi
D7 D6 D5 D4 D3 D2 D1 D0
i = 0 to 2
NOTE:
1. This applies to the case where the CKPOL bit in the UiC0 register is set to 0 (transmit data output at
the falling edge and the receive data taken in at the rising edge of the transfer clock) and the
UiLCH bit in the UiC1 register 0 (no reverse).
Figure 14.12 Transfer format
Rev. 1.12 Mar.30, 2007 ^{page 185} of 458
REJ09B0101-0112