M16C29 Datasheet, PDF (210/499 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/Tiny SERIES

M16C/29 Group
14.Serial I/O
14.1.1.4 Continuous receive mode
When the UiRRM bit (i=0 to 2) is set to 1 (continuous receive mode), the TI bit in the UiC1 register is
set to 0 (data present in the UiTB register) by reading the UiRB register. In this case, i.e., UiRRM bit is
set to 1, do not write dummy data to the UiTB register in a program. The U0RRM and U1RRM bits are
the bit 2 and bit 3 in the UCON register, respectively, and the U2RRM bit is the bit 5 in the U2C1
register.
14.1.1.5 Serial data logic switch function (UART2)
When the U2LCH bit in the U2C1 register is set to 1 (reverse), the data written to the U2TB register
has its logic reversed before being transmitted. Similarly, the received data has its logic reversed
when read from the U2RB register. Figure 14.13 shows serial data logic.
(1) When the U2LCH bit in the U2C1 register is set to 0 (no reverse)
Transfer clock ^{“H”}
“L”
TxD2 “H”
(no reverse) _{“L”}
D0 D1 D2 D3 D4 D5 D6 D7
(2) When the U2LCH bit in the U2C1 register is set to 1 (reverse)
Transfer clock ^{“H”}
“L”
TxD2 “H”
(reverse) _{“L”}
D0 D1 D2 D3 D4 D5 D6 D7
NOTE:
1. This applies to the case where the CKPOL bit in the U2C0 register is set to 0 (transmit data
output at the falling edge and the receive data taken in at the rising edge of the transfer
clock) and the UFORM bit is set to 0 (LSB first).
Figure 14.13 Serial data logic switch timing
14.1.1.6 Transfer clock output from multiple pins function (UART1)
The CLKMD1 to CLKMD0 bits in the UCON register can choose one from two transfer clock output
pins. (See Figure 14.14) This function is valid when the internal clock is selected for UART1.
MCU
TXD1 (P67)
CLKS1 (P64)
CLK1 (P65)
IN
IN
CLK
CLK
Transfer enabled
when the CLKMD0
bit in the UCON
register is set to 0
Transfer enabled
when the CLKMD0
bit in the UCON
register is set to 1
NOTES:
1. This applies to the case where the CKDIR bit in the U1MRregister is set to 0 (internal clock) and
the CLKMD1 bit in the UCON register is set to 1 (transfer clock output from multiple pins).
2. This applies to the case where U1MAP bit in PACR register is set to 0 (P67 to P64).
Figure 14.14 Transfer Clock Output From Multiple Pins
Rev. 1.12 Mar.30, 2007 ^{page 186} of 458
REJ09B0101-0112