M16C29 Datasheet, PDF (279/499 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/Tiny SERIES

M16C/29 Group
16. MULTI-MASTER I²C bus INTERFACE
16. Multi-master I²C bus Interface
The multi-master I²C bus interface is a serial communication circuit based on Philips I²C bus data transfer
format, equipped with arbitration lost detection and synchronous functions. Figure 16.1 shows a block
diagram of the multi-master I²C bus interface and Table 16.1 lists the multi-master I²C bus interface func-
tions.
The multi-master I²C bus interface consists of the S0D0 register, the S00 register, the S20 register, the
S3D0 register, the S4D0 register, the S10 register, the S2D0 register and other control circuits.
Figures 16.2 to 16.8 show the registers associated with the multi-master I²C bus.
Table 16.1 Multi-master I²C bus interface functions
Item
Format
Function
Based on Philips I²C bus standard:
7-bit addressing format
High-speed clock mode
Communication mode
Standard clock mode
Based on Philips I²C bus standard:
Master transmit
Master receive
Slave transmit
SCL clock frequency
Slave receive
16.1kHz to 400kHz (at VIIC ⁽¹⁾= 4MHz)
I/O pin
Serial data line SDAMM(SDA)
Serial clock line SDLMM(SCL)
NOTE:
1. VIIC=I²C system clock
Rev. 1.12 Mar.30, 2007 ^{page 255} of 458
REJ09B0101-0112