M16C29 Datasheet, PDF (151/499 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/Tiny SERIES

M16C/29 Group
12. Timer (Three-phase Motor Control Timer Function)
Three-phase PWM Control Register 0 ⁽¹⁾
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
INVC0
034816
After Reset
0016
Bit Symbol
Bit Name
Function
RW
INV00
Effective interrupt output
polarity select bit⁽³⁾
0: ICTB2 counter is incremented by 1 on
the rising edge of timer A1 reload control
signal
1: ICTB2 counter is incremented by 1 on
RW
the falling edge of timer A1 reload control
signal
INV01
Effective interrupt output
specification bit^{(2, 3)}
0: ICTB2 counter incremented by 1 at a
timer B2 underflow
1: Selected by INV00 bit
RW
INV02
INV03
INV04
0: Three-phase motor control timer
Mode select bit⁽⁴⁾
function unused
1: Three-phase motor control timer
RW
function (5)
0: Three-phase motor control timer output
Output control bit⁽⁶⁾
disabled (5)
1: Three-phase motor control timer output
RW
enabled
Positive and negative
phases concurrent output
disable bit
0: Simultaneous active output enabled
1: Simultaneous active output disabled
RW
Positive and negative
INV05
phases concurrent output
detect flag
0: Not detected yet
1: Already detected ⁽⁷⁾
RW
0: Triangular wave modulation mode
INV06 Modulation mode select bit⁽⁸⁾ _{1: Sawtooth wave modulation mode} (9)
RW
INV07
Software trigger select bit
Setting this bit to 1 generates a transfer
trigger. If the INV06 bit is 1, a trigger for the
dead time timer is also generated. The
RW
value of this bit when read is 0
NOTES:
1. Write to this register after setting the PRC1 bit in the PRCR register to 1 (write enable). Note also that bits INV00 to INV02,
bits INV04 and INV06 can only be rewritten when timers A1, A2, A4 and B2 are idle.
2. If this bit needs to be set to 1, set any value in the ICTB2 register before writing to it.
3. Effective when the INV11 bit in the INV1 register is 1 (three-phase mode 1). If INV11 is set to 0 (three-phase mode 0), the
ICTB2 counter is incremented by 1 each time the timer B2 underflows, regardless of whether the INV00 and INV01 bits are
set. When setting the INV01 bit to 1, the first interrupt is generated when the timer B2 underflows n-1 times, if n is the value
set in the ICTB2 counter. Subsequent interrupts are generated every n times the timer B2 underflow.
4. Setting the INV02 bit to 1 activates the dead time timer, U/V/W-phase output control circuits and ICTB2 counter.
5. When the INV02 bit is set to 1 and the INV03 bit is set to 0, U, U, V, V, W, W pins, including pins shared with other output
functions, enter a high-impedance state. When INV03 is set to 1, U/V/W corresponding pins generate the three-phase PWM
output.
6. The INV03 bit is set to 0 in the following cases:
• When reset
• When positive and negative go active (INV05 = 1) simultaneously while INV04 bit is 1
• When set to 0 by program
• When input on the SD pin changes state from “H” to “L” regardless of the value of the INVCR1 bit. (The INV03 bit cannot be
set to 1 when SD input is “L”.) INV03 is set to 0 when both bits INV05 and INV04 are set to 1.
Item
Mode
Timing at which transferred from registers
IDB0 to IDB1 to three-phase output shift
register
Timing at which dead time timer trigger is
generated when INV16 bit is 0
INV13 bit
INV06=0
Triangular wave modulation mode
Transferred only once synchronously
with the transfer trigger after writing to
registers IDB0 to IDB1
Synchronous with the falling edge of
timer A1, A2, or A4 one-shot pulse
Effective when INV11 is set to 1 and
INV06 is set to 0
INV06=1
Sawtooth wave modulation mode
Transferred every transfer trigger
Synchronous with the transfer
trigger and the falling edge of timer
A1, A2, or A4 one-shot pulse
No effect
Transfer trigger: Timer B2 underflow, write to the INV07 bit or write to the TB2 register when the INV10 bit is set to 1.
9: If the INV06 bit is set to 1, set the INV11 bit to 0 (three-phase mode 0) and set the PWCON bit to 0 (timer B2 reloaded by a
timer B2 underflow)
10. When the PFCi (i = 0 to 5) bit in the PFCR register is set to 1 (three-phase PWM output), individual pins are enabled to output.
Figure 12.26 INVC0 Register
Rev. 1.12 Mar.30, 2007 ^{page 127} of 458
REJ09B0101-0112