M16C29 Datasheet, PDF (244/499 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/Tiny SERIES

M16C/29 Group
14.2.1 SI/Oi Operation Timing
Figure 14.37 shows the SI/Oi operation timing
14. Serial I/O
"H"
SI/Oi internal clock _"L"
CLKi output ^"H"
"L"
Signal written to the "H"
SiTRR register ^"L"
SOUTi output "H"
"L"
SINi input
"H"
"L"
1.5 cycle (max) (3)
D0
D1
D2
D3
D4
D5
D6
(2)
D7
SiIC register ¹
IR bit 0
i= 3, 4
NOTES:
1. This diagram applies to the case where the SiC register bits are set as follows:
SMi2 = 0 (SOUTi output), SMi3 = 1 (SOUTi output, CLKi function), SMi4 = 0 (transmit data output at the falling edge and receive data input at the
rising edge of the transfer clock), SMi5 = 0 (LSB first) and SMi6 = 1 (internal clock)
2. When the SMi6 bit is set to 0 (internal clock), the SOUTi pin is placed in the high-impedance state after the transfer is completed.
3. If the SMi6 bit is set to 0 (internal clock), the serial I/O starts sending or receiving data a maximum of 1.5 transfer clock cycles after writing to
the SiTRR register.
Figure 14.37 SI/Oi Operation Timing
14.2.2 CLK Polarity Selection
The the SMi4 bit in the SiC register allows selection of the polarity of the transfer clock. Figure 14.38
shows the polarity of the transfer clock.
(1) When the SMi4 bit in the SiC register is set to 0
CLKi
(2)
SINi
D0 D1 D2 D3 D4 D5 D6 D7
SOUTi
D0 D1 D2 D3 D4 D5 D6 D7
(2) When the SMi4 bit in the SiC register is set to 1
CLKi
(3)
SINi
D0 D1 D2 D3 D4 D5 D6 D7
SOUTi
D0 D1 D2 D3 D4 D5 D6 D7
i=3 and 4
NOTES:
1. This diagram applies to the case where the SiC register bits are set as follows:
SMi5 = 0 (LSB first) and SMi6 = 1 (internal clock)
2. When the SMi6 bit is set to 1 (internal clock), a high level is output from the CLKi pin if not transferring data.
3 When the SMi6 bit is set to 1 (internal clock), a low level is output from the CLKi pin if not transferring data.
Figure 14.38 Polarity of Transfer Clock
Rev. 1.12 Mar.30, 2007 ^{page 220} of 458
REJ09B0101-0112