M16C29 Datasheet, PDF (170/499 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/Tiny SERIES

M16C/29 Group
13. Timer S
Waveform Generation Register j (j=0 to 7)
b15
b8
(b7)
(b0) b7
Symbol
Address
b0
G1TM0 to G1TM2 030116-030016, 030316-030216, 030516-030416
G1TM3 to G1TM5 030716-030616, 030916-030816, 030B16-030A16
G1TM6 to G1TM7 030D16-030C16, 030F16-030E16
After Reset
Indeterminte
Indeterminte
Indeterminte
Function
The base timer value is stored every
measurement timing
Setting Range RW
RO
Waveform Generation Control Register j (j=0 to 7)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
G1POCR0 to G1POCR3
031016, 031116, 031216, 031316
G1POCR4 to G1POCR7
031416, 031516, 031616, 031716
After Reset
0X00 XX002
0X00 XX002
Bit
Symbol
Bit Name
MOD0
MOD1
Operating mode
select bit
Function
RW
b1b0
0 0: Single waveform output mode
0 1: SR waveform output mode ⁽¹⁾
RW
1 0: Phase-delayed waveform
output mode
1 1: Do not set to this value
RW
(b3-b2)
IVL
RLD
(b6)
Nothing is assigned. If necessary, set to 0.
When read, their contents are undefined
Output initial value
select bit⁽⁴⁾
G1POj register value
reload timing select bit
0: "L" output as a default value
1: "H" output as a default value
RW
0: Reloads the G1POj register when
value is written
1: Reloads the G1POj register when
RW
the base timer is reset
Nothing is assigned. If necessary, set to 0.
When read, its content is undefined
INV
Inverse output function 0: Output is not inversed
select bit ⁽²⁾
1: Output is inversed
RW
NOTES :
1. This setting is enabled only for even channels. In SR waveform output mode, values written to the
corresponding odd channel (next channel after an even channel) are ignored. Even channels
provide waveform output. Odd channels provide no waveform output.
2. The inverse output function is the final step in waveform generating process. When the INV bit is set
to 1, and "H" signal is provided a default output by setting the IVL bit to 0, and an "L" signal is
provided by setting it to 1.
3. In the SR waveform output mode, set not only the even channel but also the correspoinding even
channel (next channel after the even channel).
4. To provide either "H" or "L" signal output set in the IVL bit, set the FSCj bit in the G1FS register to 0
(select waveform generating function) and IFEj bit in the G1FE register to 1 (functions for channel j
enabled). Then set the IVL bit to 0 or 1.
Figure 13.6 G1TM0 to G1TM7 Registers, and G1POCR0 to G1POCR7 Registers
Rev. 1.12 Mar.30, 2007 ^{page 146} of 458
REJ09B0101-0112