M16C29 Datasheet, PDF (305/499 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/Tiny SERIES

M16C/29 Group
16. MULTI-MASTER I²C bus INTERFACE
16.12 START/STOP Condition Detect Operation
Figure 16.18, Figure 16.19 and Table 16.10 show START/STOP condition detect operations. Bits SSC4
to SSC0 in the S2D0 register set the START/STOP conditions. The START/STOP condition can be de-
tected only when the input signal of the SCLMM and SDAMM met the following conditions: the SCL release
time, the set-up time, and the hold time (see Table 16.10). The BB flag in the S10 register is set to 1 when
the START condition is detected and it is set to 0 when the STOP condition is detected. The BB flag set and
reset timing varies between standard clock mode and high-speed clock mode. See Table 16.10.
SCL
SDA
BB flag
SCL release time
Setup time
Hold time
BB flag
set time
Figure 16.18 Start condition detection timing diagram
SCL
SDA
BB flag
SCL release time
Setup time
Hold time
BB flag
set time
Figure 16.19 Stop condition detection timing diagram
Table 16.10 Start/Stop detection timing table
Standard clock mode
SCL release time
SSC value + 1 cycle (6.25µs)
Setup time
SSC value + 1 cycle < 4.0µs (3.25µs)
2
Hold time
SSC value cycle < 4.0µs (3.0µs)
2
BB flag set/reset
SSC value - 1 +2 cycles (3.375µs)
time
2
High-speed clock mode
4 cycles (1.0µs)
2 cycles (0.5µs)
2 cycles (0.5µs)
3.5 cycles (0.875µs)
NOTE:
1. Unit : number of cycle for I²C system clock VIIC
The SSC value is the decimal notation value of bits SSC4 to SSC0. Do not set 0 or odd numbers to the SSC
setting. The values in ( ) are examples when the S2D0 register is set to 1816 at VIIC = 4 MHz.
Rev. 1.12 Mar.30, 2007 ^{page 281} of 458
REJ09B0101-0112