M16C29 Datasheet, PDF (203/499 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/Tiny SERIES

M16C/29 Group
14. Serial I/O
UART2 Special Mode Register 3
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U2SMR3
Address
037516
After Reset
000X0X0X 2
Bit
Symbol
Bit Name
Function
RW
Nothing is assigned. If necessary, set to 0.
(b0) _{When read, the content is undefined}
CKPH Clock phase set bit
0 : Without clock delay
1 : With clock delay
RW
Nothing is assigned. If necessary, set to 0.
(b2) _{When read, the content is undefined}
NODC Clock output select bit
0 : CLK2 is CMOS output
1 : CLK2 is N-channel open drain output
RW
Nothing is assigned. If necessary, set to 0.
(b4) _{When read, the content is undefined}
DL0 _{SDA2 digital delay}
setup bit
b7 b6 b5
0 0 0 : Without delay
RW
(1, 2)
0 0 1 : 1 to 2 cycle(s) of U2BRG count source
DL1
0 1 0 : 2 to 3 cycles of U2BRG count source
0 1 1 : 3 to 4 cycles of U2BRG count source
RW
1 0 0 : 4 to 5 cycles of U2BRG count source
DL2
1 0 1 : 5 to 6 cycles of U2BRG count source
1 1 0 : 6 to 7 cycles of U2BRG count source
RW
1 1 1 : 7 to 8 cycles of U2BRG count source
NOTES:
1. Bits DL2 to DL0 are used to generate a delay in SDA output by digital means during I²C bus mode. In other than I²C bus
mode,set these bits to 0002 (no delay).
2. The amount of delay varies with the load on pins SCL2 and SDA2. Also, when using an external clock, the amount of
delay increases by about 100 ns.
UART2 Special Mode Register 4
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U2SMR4
Address
037416
After Reset
0016
Bit
Symbol
Bit Name
Function
RW
STAREQ ^{Start condition}
generate bit ⁽¹⁾
0 : Clear
1 : Start
RW
RSTAREQ Restart condition
generate bit ⁽¹⁾
0 : Clear
1 : Start
RW
STPREQ ^{Stop condition}
generate bit⁽¹⁾
0 : Clear
1 : Start
RW
STSPSEL SCL2,SDA2 output
select bit
0 : Start and stop conditions not output
1 : Start and stop conditions output
RW
ACKD ACK data bit
0 : ACK
1 : NACK
RW
ACKC
ACK data output
enable bit
0 : Serial I/O data output
1 : ACK data output
RW
SCLHI
SCL2 output stop
enable bit
0 : Disabled
1 : Enabled
RW
SWC9 ^{SCL2 wait bit 3}
0 : SCL2 “L” hold disabled
1 : SCL2 “L” hold enabled
RW
NOTE:
1. Set to 0 when each condition is generated.
Figure 14.9 U2SMR3 and U2SMR4 Registers
Rev. 1.12 Mar.30, 2007 ^{page 179} of 458
REJ09B0101-0112