M16C29 Datasheet, PDF (285/499 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/Tiny SERIES

M16C/29 Group
16. MULTI-MASTER I²C bus INTERFACE
I²C0 Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
S3D0
Address
02E616
After Reset
001100002
Bit Symbol
Bit Name
Function
RW
SIM
The interrupt enable bit for 0: Disable the I²C bus interface
STOP condition detection
interrupt of STOP condition
detection
1: Enable the I²C bus interface
RW
interrupt of STOP condition
detection
WIT
The interrupt enable bit for 0: Disable the I²C bus interface
data receive completion
interrupt of data receive
completion
1: Enable the I²C bus interface
interrupt of data receive
RW
completion
When setting NACK
(ACK bit = 0), write 0
PED
SDA/port function switch
bit⁽¹⁾
0: SDA I/O pin
1: Port output pin
RW
PEC
SCL/port function switch
bit⁽¹⁾
0: SCL I/O pin
1: Port output pin
RW
The logic value monitor
0: SDA output logic value = 0
SDAM
bit of SDA output
1: SDA output logic value = 1
RO
SCLM
The logic value monitor
bit of SCL output
0: SCL output logic value = 0
1: SCL output logic value = 1
RO
ICK0
I²C bus system clock
b7 b6
0 0 : VIIC =1/2 fIIC
RW
selection bits,
0 1 : VIIC =1/4fIIC
ICK1
if bits ICK4 to ICK2 in the _{1 0 : VIIC =1/8 fIIC}
S4D0 register is 0002
1 1 : Reserved
(2)
RW
NOTE:
1. Bits PED and PEC are enabled when the ES0 bit in the S1D0 register is set to 1 (I²C bus interface enabled).
2. When the PCLK0 bit in the PCLKR register is set to 0, fIIC=f2. When the PCLK0 bit in the PCLKR register is set
to 1, fIIC=f1.
Figure 16.6 S3D0 Register
Rev. 1.12 Mar.30, 2007 ^{page 261} of 458
REJ09B0101-0112