M16C29 Datasheet, PDF (248/499 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/Tiny SERIES

M16C/29 Group
15. A/D Converter
A/D Control Register 0 ⁽¹⁾
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON0
Address
03D616
After Reset
00000XXX 2
Bit Symbol
CH0
Bit Name
Function
RW
RW
CH1
Analog input pin select bit Function varies with each operation mode RW
CH2
RW
MD0
MD1
A/D operation mode
select bit 0
b4 b3
0 0: One-shot mode or Delayed trigger
RW
mode 0,1
0 1: Repeat mode
1 0: Single sweep mode or Simultaneous
sample sweep mode
1 1: Repeat sweep mode 0 or Repeat
RW
sweep mode 1
TRG
Trigger select bit
0: Software trigger
1: Hardware trigger
RW
ADST
A/D conversion start flag
0: A/D conversion disabled
1: A/D conversion started
RW
CKS0 Frequency select bit 0
See Table 15.2
RW
NOTE:
1. If the ADCON0 register is rewritten during A/D conversion, the conversion result will be undefined.
A/D Control Register 1 ⁽¹⁾
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON1
Address
03D716
After Reset
0016
Bit Symbol
Bit Name
Function
RW
SCAN0
SCAN1
A/D sweep pin select bit
RW
Function varies with each operation mode
RW
MD2
A/D operation mode
select bit 1
0 : Other than repeat sweep mode 1
1 : Repeat sweep mode 1
RW
BITS
8/10-bit mode select bit
0 : 8-bit mode
1 : 10-bit mode
RW
CKS1 Frequency select bit 1
See Table 15.2
RW
VCUT
Vref connect Bit ⁽²⁾
0 : Vref not connected
1 : Vref connected
RW
(b7-b6)
Nothing is assigned. If necessary, set to 0.
When read, its content is 0
NOTES:
1. If the ADCON1 register is rewritten during A/D conversion, the conversion result will be undefined.
2. If the VCUT bit is reset from 0 (VREF unconnected) to 1 (VREF connected), wait for 1 µs or more before starting A/D
conversion.
A/D Control Register 2⁽¹⁾
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
ADCON2
Address
03D416
After Reset
0016
Bit Symbol
Bit Name
Function
RW
SMP
A/D conversion method
select bit
0: Without sample and hold
1: With sample and hold
RW
b2 b1
ADGSEL0
0 0: Select port P10 group
RW
A/D input group select bit ^{0 1: Select port P9 group}
1 0: Select port P0 group
ADGSEL1
1 1: Select port P1/P9 group
RW
(b3)
Reserved bit
Set to 0
RW
CKS2 Frequency select bit 2
See Table 15.2
RW
TRG1
(b7-b6)
Trigger select bit
Function varies with each operation mode RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 0
NOTS:
1. If the ADCON2 register is rewritten during A/D conversion, the conversion result will be undefined.
Figure 15.2 ADCON0 to ADCON2 Registers
Rev. 1.12 Mar.30, 2007 ^{page 224} of 458
REJ09B0101-0112