M16C29 Datasheet, PDF (28/499 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/Tiny SERIES

M16C/29 Group
1.2 Block Diagram
Figure 1.1 is a block diagram of the M16C/29 Group, 80-pin package.
1. Overview
8
8
8
8
I/O Ports
Port P0
Port P1
Port P2
Port P3
Internal Peripheral Functions
Timer (16 bits)
Output (Timer A) : 5
Input (Timer B) : 3
3-phase PWM
Timer S
( ) Input capture/
Output compare
Time measurement : 8 channels
Waveform generating : 8 channels
UART/clock synchronous SI/O
(8 bits x 3 channels)
Clock synchronous SI/O
(8 bits x 2 channels)
Multi-master I²C bus
CAN module
(1 channel)
M16C/60 Series CPU Core
System clock generator
XIN-XOUT
XCIN-XCOUT
On-chip oscillator
PLL frequency synthesizer
CRC calculation circuit
(CCITT, CRC-16)
Memory
A/D converter
(1 0 b its x 2 7 ch a n n e ls)
Watchdog timer
(15 bits)
DMAC
(2 channels)
R0H R0L
R1H R1L
R2
R3
A0
A1
FB
SB
USP
ISP
INTB
PC
FLG
ROM⁽¹⁾
RAM⁽²⁾
Multiplier
NOTES:
1. The ROM capacity varies depending on each product.
2. The RAM capacity varies depending on each product.
Figure 1.1 M16C/29 Group, 80-Pin Block Diagram
Rev. 1.12 Mar.30, 2007
REJ09B0101-0112
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