M16C29 Datasheet, PDF (221/499 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/Tiny SERIES

M16C/29 Group
14. Serial I/O
SDA2
Delay
circuit
STSPSEL=1
STSPSEL=0
ACKC=1 ACKC=0
ACKD bit
Noise
Filter
SDHI _ALS
D _{Q Arbitration}
T
Start condition
detection
Stop condition
detection
Start and stop condition generation block
SDASTSP
SCLSTSP
Transmission
register
UART2
IICM2=1
IICM=1 and
IICM2=0
Reception register
UART2
S
Q
Bus
R _busy
IICM2=1
IICM=1 and
IICM2=0
NACK
DMA0, DMA1 request
UART2 transmit,
NACK interrupt
request
DMA0
UART2 receive,
ACK interrupt request,
DMA1 request
SCL2
Noise
Filter
Falling edge
detection
IICM=0
R
I/O port Q
STSPSEL=0
Port register
(1)
Internal clock
DQ
T
DQ
T
9th bit
ACK
IICM=1UART2 _STSPSEL=1
SWC2
External
clock
CLK
control
UART2
R
9th bit falling edge
S
SWC
Start/stop condition
detection interrupt
request
This diagram applies to the case where bits SMD2 to SMD0 in the U2MR register is set to 0102 and the IICM bit in the U2SMR register
is set to 1.
IICM: Bit in the U2SMR register
IICM2, SWC, ALS, SWC2, SDHI: Bits in the U2SMR2 register
STSPSEL, ACKD, ACKC: Bits in the U2SMR4 register
NOTE:
1. If the IICM bit is set to 1, the pin can be read even when the PD7_1 bit is set to 1 (output mode).
Figure 14.22 I²C bus mode Block Diagram
Rev. 1.12 Mar.30, 2007 ^{page 197} of 458
REJ09B0101-0112