M16C29 Datasheet, PDF (177/499 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/Tiny SERIES

M16C/29 Group
13. Timer S
FFFF16
State of a counter
C00016
800016
400016
000016
IT=1 in the G1BCR0 register
(Base timer interrupt generated
by the bit 14 overflow)
1
b14 overflow signal
0
Base Timer interrupts
IT=0 in the G1BCR0 register
(Base timer interrupt generated
by the bit 15 overflow)
1
b15 overflow signal
0
Base Timer interrupt
The above applies to the following conditions.
The RST4 bit in the G1BCR0 register is set to 0 (the base timer is not reset by matching the G1BTRR register)
The RST1 bit in the G1BCR1 register is set to 0 (the base timer is not reset by matching the G1PO0 register)
Bits UD1 to UD0 in the G1BCR1 register are set to 002 (counter increment mode)
Figure 13.12 Counter Increment Mode
FFFF16
State of a counter
C00016
800016
400016
000016
IT=1 in the G1BCR0 register
(Base timer interrupt generated
by the bit 14 overflow)
b14 overflow signal ¹
0
Base Timer interrupts
IT=0 in the G1BCR0 register
(Base timer interrupt generated
by the bit 15 overflow)
b15 overflow signal ¹
0
Base Timer interrupt
Figure 13.13 Counter Increment/Decrement Mode
Rev. 1.12 Mar.30, 2007 ^{page 153} of 458
REJ09B0101-0112