M16C29 Datasheet, PDF (122/499 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/Tiny SERIES

M16C/29 Group
11. DMAC
11.2. DMA Transfer Cycles
Any combination of even or odd transfer read and write adresses is possible. Table 11.2 shows the
number of DMA transfer cycles. Table 11.3 shows the Coefficient j, k.
The number of DMAC transfer cycles can be calculated as follows:
No. of transfer cycles per transfer unit = No. of read cycles x j + No. of write cycles x k
Table 11.2 DMA Transfer Cycles
Transfer unit Access address
8-bit transfers
Even
(DMBIT= 1)
Odd
16-bit transfers
Even
(DMBIT= 0)
Odd
No. of read cycles
1
1
1
2
No. of write cycles
1
1
1
2
Table 11.3 Coefficient j, k
Internal Area
Internal ROM, RAM
No wait With wait
j1
2
SFR
1 wait
(1)
2 wait
(1)
2
3
k1
2
2
3
NOTE:
1. Depends on the set value of PM20 bit in PM2 register
Rev. 1.12 Mar.30, 2007
REJ09B0101-0112
page 98 _{of 458}