M16C29 Datasheet, PDF (391/499 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/Tiny SERIES

M16C/29 Group
21. Electrical Characteristics (Normal-version)
Table 21.2 Recommended Operating Conditions (Note 1)
Symbol
VCC
AVCC
Supply Voltage
Analog Supply Voltage
Parameter
Standard
Min. Typ.
Max.
2.7
5.5
VCC
VSS
Supply Voltage
0
AVSS Analog Supply Voltage
0
VIH
Input High ("H") P00 to P07, P10 to P17, P20 to P27, P30 to P37, P60 to P67, 0.7VCC
Voltage
P70 to P77, P80 to P87, P90 to P93, P95 to P97, P100 to P107
XIN, RESET, CNVSS
0.8VCC
When I²C bus input level is selected
SDAMM, SCLMM
When SMBUS input level is selected
0.7VCC
1.4
VIL
Input Low ("L") P00 to P07, P10 to P17, P20 to P27, P30 to P37, P60 to P67,
0
Voltage
P70 to P77, P80 to P87, P90 to P93, P95 to P97, P100 to P107
VCC
VCC
VCC
VCC
0.3VCC
XIN, RESET, CNVSS
0
When I²C bus input level is selected
0
SDAMM, SCLMM
When SMBUS input level is selected
0
IOH(peak)
Peak Output High P00 to P07, P10 to P17, P20 to P27, P30 to P37, P60 to P67,
("H") Current
P70 to P77, P80 to P87, P90 to P93, P95 to P97, P100 to P107
IOH(avg)
Average Output P00 to P07, P10 to P17, P20 to P27, P30 to P37, P60 to P67,
High ("H") Current _{P70 to P77, P80 to P87, P90 to P93, P95 to P97, P100 to P107}
IOL(peak)
Peak Output Low P00 to P07, P10 to P17, P20 to P27, P30 to P37, P60 to P67,
("L") Current
P70 to P77, P80 to P87, P90 to P93, P95 to P97, P100 to P107
IOL(avg)
Average Output P00 to P07, P10 to P17, P20 to P27, P30 to P37, P60 to P67,
Low ("L") Current _{P70 to P77, P80 to P87, P90 to P93, P95 to P97, P100 to P107}
f(XIN) Main Clock Input Oscillation Frequency⁽⁴⁾
VCC=3.0 to 5.5V
0
0.2VCC
0.3VCC
0.6
-10.0
-5.0
10.0
5.0
20
VCC=2.7 to 3.0V
0
33 X VCC-80
f(XCIN) Sub Clock Oscillation Frequency
32.768
50
f1(ROC) On-chip Oscillator Frequency 1
0.5
1
2
f2(ROC) On-chip Oscillator Frequency 2
1
2
4
f3(ROC) On-chip Oscillator Frequency 3
f(PLL) PLL Clock Oscillation Frequency⁽⁴⁾
8
16
26
VCC=3.0 to 5.5V
10
20
VCC=2.7 to 3.0V
10
33 X VCC-80
f(BCLK) CPU Operation Clock Frequency
0
20
tSU(PLL) Wait Time to Stabilize PLL Frequency Synthesizer
VCC=5.0V
20
VCC=3.0V
50
NOTES:
1. Referenced to VCC = 2.7 to 5.5V at Topr = -20 to 85 ° C / -40 to 85 ° C unless otherwise specified.
2. The mean output current is the mean value within 100ms.
3. The total IOL(peak) for all ports must be 80mA or less. The total IOH(peak) for all ports must be -80mA or less.
4. Relationship among main clock oscillation frequency, PLL clock oscillation frequency and supply voltage.
Unit
V
V
V
V
V
V
V
V
V
V
V
V
mA
mA
mA
mA
MHz
MHz
kHz
MHz
MHz
MHz
MHz
MHz
MHz
ms
ms
Main clock input oscillation frequency
PLL clock oscillation frequency
20.0
33.3 x VCC-80 MHZ
33.3 x VCC-80 MHZ
20.0
10.0
10.0
0.0
2.7 3.0
5.5
VCC[V] (main clock: no division)
0.0
2.7 3.0
5.5
VCC[V] (PLL clock oscillation)
Rev. 1.12 Mar.30, 2007 ^{page 367} of 458
REJ09B0101-0112