M16C29 Datasheet, PDF (77/499 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/Tiny SERIES

M16C/29 Group
7. Clock Generation Circuit
PLL Control Register 0 ^(1,2)
b7 b6 b5 b4 b3 b2 b1 b0
00 1
Symbol
PLC0
Address
001C16
After Reset
0001X0102
Bit
Symbol
Bit Name
Function
RW
PLC00
PLL multiplying factor
select bit
(3)
b2 b1b0
0 0 0: Do not set
0 0 1: Multiply by 2
RW
0 1 0: Multiply by 4
PLC01
0 1 1:
RW
1 0 0:
1 0 1: Do not set
PLC02
1 1 0:
RW
1 1 1:
Nothing is assigned. If necessary, set to 0.
(b3) ^{When read, the content is undefined}
(b4) ^{Reserved bit}
Set to 1
RW
(b6-b5) ^{Reserved bit}
Set to 0
RW
PLC07 Operation enable bit ⁽⁴⁾
0: PLL Off
1: PLL On
RW
NOTES:
1. Write to this register after setting the PRC0 bit in the PRCR register to 1 (write enable).
2. When the PM21 bit in the PM2 register is 1 (clock modification disable), writing to this register has no effect.
3. These three bits can only be modified when the PLC07 bit is set to 0 (PLL turned off). The value once written to
this bit cannot be modified.
4. Before setting this bit to 1 , set the CM07 bit to 0 (main clock), set bits CM17 to CM16 bits to 002 (main
clock undivided mode), and set the CM06 bit to 0 (CM16 and CM17 bits enable).
CAN0 Clock Select Register ⁽¹⁾
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CCLKR
Address
025F16
After Reset
0016
Bit Symbol
Bit Name
Function
RW
b2 b1 b0
CCLK0
0 0 0 No division
RW
0 0 1: Divide-by-2
0 1 0: Divide-by-4
CCLK1 CAN0 clock select bits⁽²⁾ 0 1 1: Divide-by-8
RW
1 0 0: Divide-by-16
1 0 1:
CCLK2
1 1 0: Inhibited
1 1 1:
RW
CCLK3
CAN0 CPU interface
sleep bit⁽³⁾
0: CAN0 CPU interface operating
1: CAN0 CPU interface in sleep
RW
(b7-b4) ^{Nothing is assigned. If necessary, set to 0. When read,}
RW
the content is 0
NOTES:
1. Write to this register after setting the PRC0 bit in the PRCR register to 1 (write enable).
2. Configuration of bits CCLK2 to CCLK0 can be done only when the Reset bit in the C0CTLR register is set to 1
(Reset/Initialization mode).
3. Before setting this bit to 1(CAN0 CPU interface in sleep), set the Sleep bit in C0CTLR register to 1 (Sleep
mode).
Figure 7.7 PLC0 Register and CCLKR register
Rev. 1.12 Mar.30, 2007
REJ09B0101-0112
page 53 of 458