M16C29 Datasheet, PDF (321/499 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/Tiny SERIES

M16C/29 Group
17.1.3.7 C0CONR Register
Figure 17.12 shows the C0CONR register.
17. CAN Module
CAN0 Configuration Register⁽²⁾
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
C0CONR
Address
021A16
After reset
Undefined
Bit symbol
Bit name
Function
RW
b3 b2 b1 b0
0 0 0 0: Divide-by-1 of fCAN
BRP
Prescaler division
ratio select bits
0 0 0 1: Divide-by-2 of fCAN
0 0 1 0: Divide-by-3 of fCAN
RW
1 1 1 0: Divide-by-15 of fCAN
1 1 1 1: Divide-by-16 of fCAN ⁽¹⁾
SAM
Sampling control bit
0: One time sampling
1: Three times sampling
RW
b7 b6 b5
0 0 0: 1Tq
0 0 1: 2Tq
PTS
Propagation time
0 1 0: 2Tq
segment control bits
RW
1 1 0: 7Tq
1 1 1: 8Tq
NOTES:
1. fCAN serves for the CAN clock. The period is decided by configuration of the CCLKi bits (i = 0 to 2) in the CCLKR register.
2. Set the C0CONR register only when the CAN module is in CAN reset / initialization mode.
(b15)
(b8)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
C0CONR
Address
021B16
After Reset
Undefined
Bit symbol
Bit name
Function
RW
b2 b1b0
0 0 0: Do not set
Phase buffer
0 0 1: 2Tq
PBS1 segment 1
0 1 0: 3Tq
RW
control bits
1 1 0: 7Tq
1 1 1: 8Tq
b5 b4 b3
0 0 0: Do not set
Phase buffer
0 0 1: 2Tq
PBS2 segment 2
0 1 0: 3Tq
RW
control bits
1 1 0: 7Tq
1 1 1: 8Tq
b7 b6
Resynchronization 0 0: 1Tq
SJW
jump width
0 1: 2Tq
RW
control bits
1 0: 3Tq
1 1: 4Tq
Figure 17.12 C0CONR Register
Rev. 1.12 Mar.30, 2007 ^{page 297} of 458
REJ09B0101-0112