M16C29 Datasheet, PDF (169/499 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/Tiny SERIES

M16C/29 Group
13. Timer S
Time Measurement Control Register j (j=0 to 7)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
G1TMCR0 to G1TMCR3
G1TMCR4 to G1TMCR7
Address
031816, 031916, 031A16, 031B16
031C16, 031D16, 031E16, 031F16
After Reset
0016
0016
Bit
Symbol
Bit Name
Function
RW
b1 b0
CTS0
0 0: No time measurement
RW
Time measurement
0 1: Rising edge
trigger select bit
CTS1
1 0: Falling edge
RW
1 1: Both edges
b3 b2
DF0
0 0: No digital filter
RW
Digital filter function
0 1: Do not set to this value
select bit
DF1
1 0: fBT1
1 1: f1 or f2 ⁽¹⁾
RW
Gate function
GT _{select bit (2)}
Gate function clear
GOC _{select bit (2, 3, 4)}
GSC
Gate function clear
bit ^{(2, 3)}
0: Gate function is not used
1: Gate function is used
RW
0: Not cleared
1: The gate is cleared when the base RW
timer matches the G1POk register
The gate is cleared by setting the
GSC bit to 1
RW
Prescaler function
0: Not used
PR _{select bit (2)}
1: Used
RW
NOTES:
1. When the PCLK0 bit in the PCLKR register is set to 0, the count source is f2 cycles. And when the
PCLK0 bit is set to 1, the count source is f1 cycles.
2. These bits are in registers G1TMCR6 and G1TMCR7. Set all bits 4 to 7 in registers G1TMCR0 to
G1TMCR5 to 0.
3. These bits are enabled when the GT bit is set to 1.
4. The GOC bit is set to 0 after the gate function is cleared. See Figure 13.7 for details on the G1POk
register (k=4 when j=6 and k=5 when j=7).
Time Measurement Prescale Register j (j=6,7)⁽¹⁾
b7
b0
Symbol
Address
G1TPR6 to G1TPR7 032416, 032516
After Reset
0016
Function
Setting Range RW
As the setting value is n, time is measured when-
ever a trigger input is counted by n+1 ⁽²⁾
0016 to FF16
RW
NOTES:
1. The G1TPR6 to G1TPR7 registers reflect the base timer value, synchronizing with the count source
fBT1 cycles.
2. The first prescaler, after the PR bit in the G1TMCRj register is changed from 0 (not used) to 1
(used), may be divided by n, rather than n+1. The subsequent prescaler is divided by n+1.
Figure 13.5 G1TMCR0 to G1TMCR7 Registers, and G1TPR6 to G1TPR7 Registers
Rev. 1.12 Mar.30, 2007 ^{page 145} of 458
REJ09B0101-0112