M16C29 Datasheet, PDF (111/499 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/Tiny SERIES

M16C/29 Group
9. Interrupts
9.9 CAN0 Wake-up Interrupt
CAN0 wake-up interrupt occurs when a falling edge is input to CRX. The CAN0 wake-up interrupt is en-
abled when the PortEn bit is set to 1 (CTX/CRX function) and Sleep bit is set to 1(Sleep mode enabled) in
the C0CTLR register. Figure 9.13 shows the block diagram of the CAN0 wake-up interrupt.
Sleep bit in C0CTLR register
PortEn bit in C0CTLR register
CRX
C01WKIC register
Interrupt control circuit
Figure 9.13 CAN0 Wake-up Interrupt Block Diagram
CAN0 wake-up
interrupt request
9.10 Address Match Interrupt
An address match interrupt request is generated immediately before executing the instruction at the ad-
dress indicated by the RMADi register (i=0 to 1). Set the start address of any instruction in the RMADi
register. Use bits AIER1 and AIER0 in the AIER register to enable or disable the interrupt. Note that the
address match interrupt is unaffected by the I flag and IPL. For address match interrupts, the value of the
PC that is saved to the stack area varies depending on the instruction being executed (refer to “Saving
Registers”).
(The value of the PC that is saved to the stack area is not the correct return address.) Therefore, follow one
of the methods described below to return from the address match interrupt.
• Rewrite the content of the stack and then use the REIT instruction to return.
• Restore the stack to its previous state before the interrupt request was accepted by using the POP or
similar other instruction and then use a jump instruction to return.
Table 9.6 shows the value of the PC that is saved to the stack area when an address match interrupt
request is accepted.
aFigure 9.14 shows registers AIER, RMAD0, and RMAD1.
Rev. 1.12 Mar.30, 2007
REJ09B0101-0112
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