M16C29 Datasheet, PDF (141/499 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/Tiny SERIES

M16C/29 Group
12. Timer B
12.2 Timer B
Figure 12.15 shows a block diagram of the timer B. Figures 12.16 and 12.17 show registers related to the
timer B.
Timer B supports the following four modes. Use bits TMOD1 and TMOD0 in the TBiMR register (i = 0 to 2)
to select the desired mode.
• Timer mode: The timer counts the internal count source.
• Event counter mode: The timer counts the external pulses or overflows and underflows of other timers.
• Pulse period/pulse width measurement mode: The timer measures the pulse period or pulse width of
external signal.
• A/D trigger mode: The timer starts counting by one trigger until the count value becomes 000016.
This mode is used together with simultaneous sample sweep mode or delayed trigger mode 0 of A/D
converter to start A/D conversion.
Clock source selection
f1 or f2
f8
f32
fC32
• Timer mode
• Pulse period/, pulse width measuring mode
• A/D trigger mode
Clock selection
• Event counter
Data bus high-order bits
Data bus low-order bits
Low-order 8 bits
Reload register
High-order 8 bits
Counter
TBiIN
(i = 0 to 2)
Polarity switching,
edge pulse
Can be selected in
onlyevent counter mode
TBj overflow (1)
(j = i – 1, except j = 2 if i = 0)
NOTE:
1. Overflow or underflow.
TABSR register
Counter reset circuit
TBi
Timer B0
Timer B1
Timer B2
Address
039116 - 039016
039316 - 039216
039516 - 039416
TBj
Timer B2
Timer B0
Timer B1
Figure 12.15 Timer B Block Diagram
Timer Bi Mode Register (i=0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
TB0MR to TB2MR 039B16 to 039D16
After Reset
00XX00002
NOTES:
1. Timer B0.
2. Timer B1, Timer B2.
Bit Symbol
TMOD0
TMOD1
MR0
MR1
MR2
Bit Name
Operation mode select bit
Function
b1 b0
0 0 : Timer mode or A/D trigger mode
0 1 : Event counter mode
1 0 : Pulse period measurement mode,
pulse width measurement mode
1 1 : Do not set
Function varies with each operation
mode
MR3
TCK0
TCK1
Count source select bit
Function varies with each operation
mode
RW
RW
RW
RW
RW
RW(1)
(2)
RO
RW
RW
Figure 12.16 TB0MR to TB2MR Registers
Rev. 1.12 Mar.30, 2007 ^{page 117} of 458
REJ09B0101-0112