M16C29 Datasheet, PDF (232/499 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/Tiny SERIES

M16C/29 Group
14. Serial I/O
14.1.4.1 Clock Phase Setting Function
One of four combinations of transfer clock phases and polarities can be selected using the CKPH bit
in the U2SMR3 register and the CKPOL bit in the U2C0 register.
Make sure the transfer clock polarity and phase are the same for the master and slave to communi-
cate.
14.1.4.1.1 Master (Internal Clock)
Figure 14.27 shows the transmission and reception timing in master (internal clock).
14.1.4.1.2 Slave (External Clock)
Figure 14.28 shows the transmission and reception timing (CKPH=0) in slave (external clock) while
Figure 14.29 shows the transmission and reception timing (CKPH=1) in slave (external clock).
Clock output
"H"
(CKPOL=0, CKPH=0) ^"L"
Clock output
"H"
(CKPOL=1, CKPH=0) _"L"
Clock output
"H"
(CKPOL=0, CKPH=1) _"L"
Clock output
"H"
(CKPOL=1, CKPH=1) "L"
Data output timing ^"H"
"L"
Data input timing
D0
D1
D2
D3
D4
D5
D6
D7
Figure 14.27 Transmission and Reception Timing in Master Mode (Internal Clock)
Rev. 1.12 Mar.30, 2007 ^{page 208} of 458
REJ09B0101-0112