M16C29 Datasheet, PDF (123/499 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/Tiny SERIES

M16C/29 Group
11. DMAC
11.3 DMA Enable
When a data transfer starts after setting the DMAE bit in the DMiCON register (i = 0, 1) to 1 (enabled), the
DMAC operates as follows:
(a) Reload the forward address pointer with the SARi register value when the DSD bit in DMiCON register
is 1 (forward) or the DARi register value when the DAD bit in the DMiCON register is 1 (forward).
(b) Reload the DMAi transfer counter with the DMAi transfer counter reload register value.
If the DMAE bit is set to 1 again while it remains set, the DMAC performs the above operation. However,
if a DMA request may occur simultaneously when the DMAE bit is being written, follow the steps below.
(1) Write 1 to bits DMAE and DMAS in DMiCON register simultaneously.
(2) Make sure that the DMAi is in an initial state as described above (a) and (b) by program.
If the DMAi is not in an initial state, the above steps should be repeated.
11.4 DMA Request
The DMAC can generate a DMA request as triggered by the cause of request that is selected with the DMS
bit and bits DSEL3 to DSEL0 in the DMiSL register (i = 0, 1) on either channel. Table 11.4 shows the timing
at which the DMAS bit changes state.
Whenever a DMA request is generated, the DMAS bit is set to 1 (DMA requested) regardless of whether or
not the DMAE bit is set. If the DMAE bit was set to 1 (enabled) when this occurred, the DMAS bit is set to
0 (DMA not requested) immediately before a data transfer starts. This bit cannot be set to 1 by program (it
can only be set to 0).
The DMAS bit may be set to 1 when the DMS or the DSEL3 to DSEL0 bits change state. Therefore, always
be sure to set the DMAS bit to 0 after changing the DMS or the DSEL3 to DSEL0 bits.
Because if the DMAE bit is set to 1, a data transfer starts immediately after a DMA request is generated, the
DMAS bit in almost all cases is 0 when read by program. Read the DMAE bit to determine whether the
DMAC is enabled.
Table 11.4 Timing at Which the DMAS Bit Changes State
DMA Factor
DMAS Bit in the DMiCON Register
Timing at which the bit is set to 1 Timing at which the bit is set to 0
Software trigger
When the DSR bit in the DMiSL
register is set to 1
• Immediately before a data transfer starts
• When set by writing 0 by program
Peripheral function
When the interrupt control register
for the peripheral function that is
selected by bits DSEL3 to DSEL0
and the DMS bit in the DMiSL
register has its IR bit set to 1
Rev. 1.12 Mar.30, 2007
REJ09B0101-0112
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