M16C29 Datasheet, PDF (187/499 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/Tiny SERIES

M16C/29 Group
13. Timer S
(1) Free-running operation
(The RST4, RST2, and RST1 bits in the G1BCR0 and G1BCR1 registers are set to 0)
FFFF16
Base timer
m
000016
m
fBT1
65536-m
fBT1
OUTC1j pin
G1IRj bit
Inverse
Inverse
65536
Return to default output level
fBT1
When setting to 0,
write 0 by program
j=0 to 7
m : Setting value of the G1POj register
G1IRj bit : Bits in the G1IR register
The above applies under the following conditions.
-The IVL bit in the G1POCRj register is set to 0 ("L" output as a default value) and the INV bit is set to 0
(not inversed).
-Bits UD1 to UD0 are set to 002 (counter increment mode).
(2) The base timer is reset when the base timer matches either following register
(a) G1PO0 (enabled by setting bit RST1 to 1, and bits RST4 and RST2 to 0), or
(b) G1BTRR (enabled by setting bit RST4 to 1, and bits RST2 and RST1 to 0)
Base timer
FFFF16
n+2
m
000016
m
fBT1
n+2-m
fBT1
OUTC1j pin
G1IRj bit
Inverse
Inverse
n+2
fBT1 ^{Write 0 by program}
if setting to 0
Inverse
Return to default
output level
j=1 to 7
m : Setting value of the G1POj register
n: Setting value of either G1PO0 register or G1BTRR register
G1IRj bit : Bits in the G1IR register
The above applies under the following conditions.
-The IVL bit in the G1POCRj register is set to 0 ("L" output as a default value) and the INV
bit is set to 0 (not inversed).
-Bits UD1 to UD0 are set to 002 (counter increment mode).
Figure 13.22 Single-phase Waveform Output Mode
Rev. 1.12 Mar.30, 2007 ^{page 163} of 458
REJ09B0101-0112