M16C29 Datasheet, PDF (327/499 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/Tiny SERIES

M16C/29 Group
17. CAN Module
17.3 Configuration of the CAN Module System Clock
The M16C/29 Group has a CAN module system clock select circuit.
Configuration of the CAN module system clock can be done through manipulating the CCLKR register and
the BRP bit in the C0CONR register.
For the CCLKR register, refer to 7. Clock Generation Circuit.
Figure 17.19 shows a block diagram of the clock generation circuit of the CAN module system.
Divide-by-1 ^(undivided)
CAN module _Divide-by-2
Prescaler
f1
system clock Divide-by-4
divider
Divide-by-8
Value: 1, 2, 4, 8, 16 Divide-by-16
fCAN
1/2
Baud rate
prescaler
division value
CCLKR register
:P+1
CAN module
fCAN: CAN module system clock
P:
The value written in the BRP bit of the C0CONR register. P = 0 to 15
fCANCLK: CAN communication clock fCANCLK = fCAN/2(P + 1)
fCANCLK
Figure 17.19 Block Diagram of CAN Module System Clock Generation Circuit
17.3.1 Bit Timing Configuration
The bit time consists of the following four segments:
• Synchronization segment (SS)
This serves for monitoring a falling edge for synchronization.
• Propagation time segment (PTS)
This segment absorbs physical delay on the CAN network which amounts to double the total sum
of delay on the CAN bus, the input comparator delay, and the output driver delay.
• Phase buffer segment 1 (PBS1)
This serves for compensating the phase error. When the falling edge of the bit falls later than
expected, the segment can become longer by the maximum of the value defined in SJW.
• Phase buffer segment 2 (PBS2)
This segment has the same function as the phase buffer segment 1. When the falling edge of the
bit falls earlier than expected, the segment can become shorter by the maximum of the value
defined in SJW.
Figure 17.20 shows the bit timing.
Bit time
SS
PTS
PBS1
PBS2
The range of each segment: Bit time = 8 to 25Tq
SS = 1Tq
PTS = 1Tq to 8Tq
PBS1 = 2Tq to 8Tq
PBS2 = 2Tq to 8Tq
SJW = 1Tq to 4Tq
SJW
SJW
Sampling point
Configuration of PBS1 and PBS2:
PBS1 ≥ PBS2
PBS1 ≥ SJW
PBS2 ≥ 2 when SJW = 1
PBS2 ≥ SJW when 2 ≤ SJW ≤ 4
Figure 17.20 Bit Timing
Rev. 1.12 Mar.30, 2007 ^{page 303} of 458
REJ09B0101-0112