M16C29 Datasheet, PDF (65/499 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/Tiny SERIES

M16C/29 Group
5. Resets
5.5.1 Low Voltage Detection Interrupt
If the D40 bit in the D4INT register is set to 1 (low voltge detection interrupt enabled), a low voltage
detection interrupt request is generated when voltage applied to the VCC pin is above or below Vdet4.
The low voltage detection interrupt shares the same interrupt vector with watchdog timer interrupt and
oscillation stop, re-oscillation detection interrupt.
Set the D41 bit in the D4INT register to 1 (enabled) to use the low voltage detection interrupt to exit stop
mode, set the D41 bit in the D4INT register to 1 (enable).
The D42 bit in the D4INT register is set to 1 (above or below Vdet4 detected) as soon as voltage applied
to the VCC pin goes above or below Vdet4 due to the voltage change. When the D42 bit setting changes
0 to 1, a low voltage detection interrupt is generated. Set the D42 bit to 0 (not detected) by program.
However, when the D41 bit is set to 1 and the MCU is in stop mode, a low voltage detection interrupt
request is generated, regardless of the D42 bit setting, if voltage applies to the VCC pin is detected to rise
above or drop below Vdet4. The MCU then exits stop mode.
Table 5.2 shows how a low voltage detection interrupt request is generated.
Bits DF1 and DF0 in the D4INT register determine sampling period that detects voltage applied to the
VCC pin rises above or drops below Vdet4. Table 5.3 shows sampling periods.
Table 5.2 Voltage Detection Interrupt Request Generation Conditions
Operation Mode VC27 bit
D40 bit
D41 bit
D42 bit
CM02 bit
VC13 bit
Normal
operation
mode(1)
Wait mode
(2)
1
1
0 to 1
0 to 1
0 to 1 ⁽³⁾
1 to 0 ⁽³⁾
0
0 to 1 (3)
1 to 0 ₍₃₎
1
0 to 1
Stop mode
(2)
1
0
0 to 1
– : 0 or 1
NOTES:
1. The status except the wait mode and stop mode is handled as the normal mode. (Refer to 7. Clock generating circuit)
2. Refer to 5.5.2 Limitations on stop mode and 5.5.3 Limitations on wait mode.
3. An interrupt request for voltage reduction is generated a sampling time after the value of the VC13 bit has changed.
Refer to the Figure 5.9 for details.
Table 5.3 Sampling Clock Periods
CPU
clock
(MHz)
Sampling clock (µs)
DF1 to DF0=00
DF1 to DF0=01
DF1 to DF0=10
DF1 to DF0=11
(CPU clock divided by 8) (CPU clock divided by 16) (CPU clock divided by 32) (CPU clock divided by 64)
16
3.0
6.0
12.0
24.0
Rev. 1.12 Mar.30, 2007
REJ09B0101-0112
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