M16C29 Datasheet, PDF (309/499 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/Tiny SERIES

M16C/29 Group
16. MULTI-MASTER I²C bus INTERFACE
SCL
SDA
BB flag
Bit reset signal
Related bits
MST
TRX
1.5 VIIC cycle
Figure 16.21 The bit reset timing (The STOP condition detection)
SCL
SDA
BB flag
Bit reset signal
Related bits
BC2 - BC0
TRX (in slave mode)
Figure 16.22 The bit reset timing (The START condition detection)
SCL
PIN bit
Bit reset signal
Bit set signal
2VIIC cycle
1VIIC cycle
The bits referring
to reset
BC0 - BC2
MST(When in arbitration lost)
TRX(When in NACK receive in slave
transmit mode)
The bits referring _{TRX(ALS=0 meanwhile the slave}
to set _{receive R/W bit = 1}
Figure 16.23 Bit set/reset timing ( at the completion of data transfer)
Rev. 1.12 Mar.30, 2007 ^{page 285} of 458
REJ09B0101-0112