M16C29 Datasheet, PDF (167/499 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/Tiny SERIES

M16C/29 Group
13. Timer S
Divider Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
G1DV
Address
032A16
Function
Divide f1, f2 or two-phase pulse input by (n+1)
for fBT1 clock cycles generation.
n: the setting value of the G1DV register
After Reset
0016
Setting range
RW
0016 to FF16
RW
Base Timer Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
0
0
0
Symbol
G1BCR1
Bit
Symbol
Bit Name
Address
032316
After Reset
0016
Function
RW
(b0) ^{Reserved bit}
Set to 0
RW
RST1
Base timer reset
cause select bit 1
RST2
Base timer reset
cause select bit 2
0: The base timer is not reset by
matching the G1PO0 register
1: The base timer is reset by matching
RW
with the G1PO0 register ⁽¹⁾
0: The base timer is not reset by
applying "L" to the INT1 pin
1: The base timer is reset by applying "L"
RW
to the INT1 pin
(b3) Reserved bit
Set to 0
RW
BTS
UD0
UD1
Base timer start bit
0: Base timer is reset
1: Base timer starts counting
RW
b6b5
0 0: Counter increment mode
RW
Counter increment/
decrement control bit
0 1: Counter increment/decrement mode
1 0: Two-phase pulse signal processing
mode
RW
1 1: Do not set to this value
(b7) ^{Reserved bit}
Set to 0
RW
NOTS:
1. The base timer is reset two fBT1 clock cycles after the base timer matches the value set in the
G1PO0 register. (See Figure 13.7 for details on the G1PO0 register) When the RST1 bit is set to 1,
the value of the G1POj register (j=1 to 7) for the waveform generating function must be set to a
value smaller than that of the G1PO0 register.
When the RST1 bit is set to 1, set the RST4 bit in the G1BCR0 register to 0.
Figure 13.3 G1DV Register and G1BCR1 Register
Rev. 1.12 Mar.30, 2007 ^{page 143} of 458
REJ09B0101-0112